diff --git a/demo/Makefile b/demo/Makefile
index eac8a3b..ec591dc 100644
--- a/demo/Makefile
+++ b/demo/Makefile
@@ -23,7 +23,8 @@ ML_RTL =					\
 	../rtl/top.v				\
 	../rtl/sequencer.v			\
 	../rtl/compute.v			\
-	../rtl/memory.v
+	../rtl/memory.v             \
+	../rtl/spi_client.v
 
 #####################################################################
 
diff --git a/demo/mlaccel.pcf b/demo/mlaccel.pcf
index f33a776..a1b8236 100644
--- a/demo/mlaccel.pcf
+++ b/demo/mlaccel.pcf
@@ -1,12 +1,12 @@
 set_io clock      35
 
-set_io qpi_csb     2
-set_io qpi_clk     4
+set_io spi_csb     2
+set_io spi_clk     46
 
-set_io qpi_io0    47
-set_io qpi_io1    45
-set_io qpi_io2     3
-set_io qpi_io3    48
+set_io spi_mosi    44
+set_io spi_miso    47
 
-set_io qpi_rdy    46
-set_io qpi_err    44
+set_io spi_rdy     45
+set_io spi_err     48
+
+# 
diff --git a/pi/README.md b/pi/README.md
new file mode 100644
index 0000000..ff3f9f5
--- /dev/null
+++ b/pi/README.md
@@ -0,0 +1,46 @@
+# Raspberry Pi Support
+
+## Run the mlaccel testbench with Python
+
+Enable spi with raspi-config:
+
+* spidev for spi comms
+
+Install Python modules spidev and RPi.GPIO:
+
+* sudo pip install spidev
+* sudo pip install RPi.GPIO
+
+Connect the Pi's SPI pins to the pins defined in the [UP5k dev board's pcf](../demo/mlaccel.pcf).
+
+![pinout](pinout.jpeg)
+
+Run the test:
+
+    python spi_test.py
+
+## Camera SPI Demo
+
+This demo will eventually stream video to the mlaccel core over SPI. For now it just
+captures frames and sends the raw data over SPI to an imaginary receiver.
+
+Install opencv the easy way:
+
+    sudo apt-get update
+    sudo apt-get install python-opencv
+
+Install Python modules picamera and spidev:
+
+    sudo pip install "picamera[array]"
+    sudo pip install spidev
+
+Enable interfaces with raspi-config:
+
+* enable camera for camera module
+* spidev for spi comms
+
+Now [cam_to_spi.py](cam_to_spi.py) should:
+
+* read a frame from the camera
+* resize according to the resolution set by export_resolution
+* send the frame row by row over SPI
diff --git a/pi/cam_to_spi.py b/pi/cam_to_spi.py
new file mode 100644
index 0000000..e56910b
--- /dev/null
+++ b/pi/cam_to_spi.py
@@ -0,0 +1,57 @@
+# import the necessary packages
+from picamera.array import PiRGBArray
+from picamera import PiCamera
+import spidev
+import time
+import cv2
+
+# initialize the camera and grab a reference to the raw camera capture
+camera = PiCamera()
+
+export_resolution = (16, 16)
+camera_res = (32, 32)
+
+camera.resolution = camera_res
+camera.framerate = 32
+rawCapture = PiRGBArray(camera, size=camera_res)
+
+# allow the camera to warmup
+time.sleep(0.1)
+
+
+import spidev
+spi = spidev.SpiDev()
+spi.open(0, 0)
+spi.max_speed_hz = 8000000  
+
+# capture frames from the camera
+time_start = time.time()
+frames = 0
+for frame in camera.capture_continuous(rawCapture, format="bgr", use_video_port=True):
+        # grab the raw NumPy array representing the image, then initialize the timestamp
+    # and occupied/unoccupied text
+    image = frame.array
+
+    #grey scale
+    image = cv2.cvtColor(image, cv2.COLOR_BGR2GRAY)
+
+    # resize
+    if export_resolution != camera_res:
+        image = cv2.resize(image, dsize=export_resolution, interpolation=cv2.INTER_CUBIC)
+
+    #cv2.imshow("Frame", image)
+    key = cv2.waitKey(1) & 0xFF
+
+    #print(image[0])
+    for row in image:
+        spi.xfer(row.tolist())
+    # clear the stream in preparation for the next frame
+    rawCapture.truncate(0)
+
+    # if the `q` key was pressed, break from the loop
+    if key == ord("q"):
+        break
+    frames += 1
+    if frames % 100 == 0:
+        print(time.time() - time_start)
+        time_start = time.time()
diff --git a/pi/demo.hex b/pi/demo.hex
new file mode 100644
index 0000000..de33a37
--- /dev/null
+++ b/pi/demo.hex
@@ -0,0 +1,2573 @@
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diff --git a/pi/demo_out.hex b/pi/demo_out.hex
new file mode 100644
index 0000000..5340e6e
--- /dev/null
+++ b/pi/demo_out.hex
@@ -0,0 +1,394 @@
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diff --git a/pi/pinout.jpeg b/pi/pinout.jpeg
new file mode 100644
index 0000000..f4830e3
Binary files /dev/null and b/pi/pinout.jpeg differ
diff --git a/pi/spi_test.py b/pi/spi_test.py
new file mode 100644
index 0000000..75b297a
--- /dev/null
+++ b/pi/spi_test.py
@@ -0,0 +1,210 @@
+MAX_ADDRESS = 1024 * 128
+MAX_DATA = 1024
+PRINT_ACK = False # print the ack waits....
+
+# setup SPI
+import spidev
+spi = spidev.SpiDev()
+spi.open(0, 0)
+spi.max_speed_hz = 8000000  
+spi.mode = 0b11
+
+# toggle CS pin manually as writing and reading in the same cycle 
+import RPi.GPIO as GPIO
+GPIO.setwarnings(False)
+GPIO.setmode(GPIO.BOARD)
+cs_pin = 22
+GPIO.setup(cs_pin, GPIO.OUT)
+GPIO.output(cs_pin, GPIO.HIGH)    
+
+# utility functions
+def get_cursor_low_high(cursor):
+    cursor_low  = cursor & 0xFF 
+    cursor_high = cursor >> 8
+    return cursor_low, cursor_high
+
+def chunks(l, n):
+    """Yield successive n-sized chunks from l."""
+    for i in range(0, len(l), n):
+        yield l[i:i + n]
+
+def spi_start():
+    GPIO.output(cs_pin, GPIO.LOW)    
+
+def spi_stop():
+    GPIO.output(cs_pin, GPIO.HIGH)    
+
+# core returns 0xFF as a busy signal. Wait till returns 0
+def get_ack(print_ack=PRINT_ACK):
+    if print_ack:
+        print("ack "),
+
+    count = 0
+    while True:
+        data = spi.readbytes(1)
+        # mlaccel core returns 0 when working, 0xFF when done
+        if data == [0]:
+            break;
+        # wait up to 10 cycles before giving up
+        count += 1
+        if print_ack and (count % 10 == 0):
+            print("."),
+
+    if print_ack:
+        print("")
+
+def spi_wait():
+    spi.readbytes(1)
+
+# send an amount of data
+def send_data(cursor, data):
+    assert cursor <= MAX_ADDRESS
+    # send the data to the buffer
+    d_len = len(data)
+    assert d_len <= MAX_DATA
+    spi_start()
+    spi.xfer([0x21])
+    spi.xfer(data)
+    spi_stop()
+
+    # get the buffer written to memory
+    spi_start()
+    cursor_low, cursor_high = get_cursor_low_high(cursor >> 1)
+    spi.xfer([0x23, cursor_low, cursor_high, d_len >> 2])
+    spi_wait()
+    # wait for data to be written
+    get_ack()
+    spi_stop()
+
+# read an amount of data
+def get_data(cursor, d_len):
+    assert cursor <= MAX_ADDRESS
+    assert d_len <= MAX_DATA
+    # write the address where we want to read
+    spi_start()
+    cursor_low, cursor_high = get_cursor_low_high(cursor >> 1)
+    spi.xfer([0x24, cursor_low, cursor_high, d_len >> 2])
+    spi_wait()
+    # wait for data to become ready
+    get_ack()
+    spi_stop()
+
+    # read it
+    spi_start()
+    spi.xfer([0x22])
+    spi_wait()
+    data = spi.readbytes(d_len)
+    spi_stop()
+    return data
+
+# start and wait for kernel
+def start_kernel():
+    spi_start()
+    spi.xfer([0x25])
+    spi.xfer([0x00, 0x00])
+    spi_stop()
+
+def wait_for_kernel():
+    spi_start()
+    spi.xfer([0x20])
+    spi_wait()
+    get_ack(print_ack=True)
+    spi_stop()
+
+# random write/read test
+def random_write_read_test():
+    import random
+    count = 0
+    while True:
+        print(count)
+        count += 1
+        for cursor in range(255):
+            rand_data = [ random.randint(0, 255), random.randint(0,255) ]
+            send_data(cursor, rand_data)
+            rx_data = get_data(cursor, len(rand_data))
+            assert(rx_data == rand_data)
+
+# check ability to write and read up to 1024 bytes
+def long_data_test(num_tests, chunk_len):
+    data = range(chunk_len)
+    data = [d % 256 for d in data ]
+
+    print("writing")
+    print("-" * 50)
+    cursor = 0
+    for t in range(num_tests):
+        print("uploading %d bytes to %05x" % (chunk_len, cursor))
+        send_data(cursor, data)
+        cursor += chunk_len
+
+    print("reading")
+    print("-" * 50)
+    cursor = 0
+    for cursor in range(num_tests):
+        print("downloading %d bytes from %05x" % (chunk_len, cursor))
+        rx_data = get_data(cursor, chunk_len)
+        assert(rx_data == data)
+        cursor += chunk_len
+
+    print("success")
+
+
+if __name__ == '__main__':
+    chunk_size = 1024
+    assert(chunk_size <= MAX_DATA)
+
+#    long_data_test(128, chunk_size)
+#    exit(0)
+
+    # prepare data
+    data_in = []
+    with open("demo.hex") as data_in_fh:
+        data_in_fh.readline()
+        for line in data_in_fh.readlines():
+            bytes_4 = [int(b, 16) for b in line.strip().split(' ')]
+            data_in += bytes_4
+
+    # upload kernel
+    print("uploading demo kernel:")
+    cursor = 0
+    for chunk in chunks(data_in, chunk_size):
+        chunk_len = len(chunk)
+        print("> uploading %4d bytes to %05x" % (chunk_len, cursor))
+        send_data(cursor, chunk)
+        cursor += chunk_len
+
+    # check data is valid
+    print("readback:")
+    cursor = 0
+    for chunk in chunks(data_in, chunk_size):
+        chunk_len = len(chunk)
+        print("< downloading %4d bytes from %05x" % (chunk_len, cursor))
+        data = get_data(cursor, chunk_len)
+        assert(data == chunk)
+        cursor += chunk_len
+
+    # run and wait for the kernel to finish
+    print("start kernel")
+    start_kernel()
+    print("wait kernel")
+    wait_for_kernel()
+
+    # prepare comparison data
+    data_out = []
+    with open("demo_out.hex") as data_out_fh:
+        data_out_fh.readline()
+        for line in data_out_fh.readlines():
+            bytes_16 = [int(b, 16) for b in line.strip().split(' ')]
+            data_out += bytes_16
+
+    # check results are valid
+    print("checking results:")
+    cursor = 0x00010000 
+    for chunk in chunks(data_out, chunk_size):
+        chunk_len = len(chunk)
+        print("< downloading %4d bytes from %05x" % (chunk_len, cursor))
+        data = get_data(cursor, chunk_len)
+        assert(data == chunk)
+        cursor += chunk_len
+
+    print("success")
diff --git a/rtl/Makefile b/rtl/Makefile
index 137c3ca..085baa4 100644
--- a/rtl/Makefile
+++ b/rtl/Makefile
@@ -5,10 +5,17 @@ all: testbench
 	sed '/^TRACE/ ! d; s/^[^:]*: //;' < testbench.log > testbench.trace
 	cmp ../sim/demo.trace testbench.trace
 
-testbench: testbench.v top.v memory.v sequencer.v compute.v
-	iverilog -DTRACE -s testbench -o testbench testbench.v top.v memory.v sequencer.v compute.v $(shell yosys-config --datdir/ice40/cells_sim.v)
+formal_spi: spi_client.v
+	sby -f spi.sby
+
+testbench_simple: testbench_simple.v top.v memory.v sequencer.v compute.v spi_client.v
+	iverilog -DTRACE -s testbench -o testbench_simple testbench_simple.v top.v memory.v sequencer.v compute.v spi_client.v $(shell yosys-config --datdir/ice40/cells_sim.v)
+	vvp -N testbench_simple
+
+testbench: testbench.v top.v memory.v sequencer.v compute.v spi_client.v
+	iverilog -DTRACE -s testbench -o testbench testbench.v top.v memory.v sequencer.v compute.v spi_client.v $(shell yosys-config --datdir/ice40/cells_sim.v)
 
 clean:
-	rm -f testbench testbench.vcd testbench.log testbench.trace
+	rm -f testbench testbench_simple testbench.vcd testbench.log testbench.trace
 
 .PHONY: all clean
diff --git a/rtl/cmd_filter.txt b/rtl/cmd_filter.txt
new file mode 100644
index 0000000..22a8cac
--- /dev/null
+++ b/rtl/cmd_filter.txt
@@ -0,0 +1,7 @@
+20 = status
+21 = wbuf 
+22 = rbuf 
+23 = wmem 
+24 = rmem 
+25 = run  
+26 = stop 
diff --git a/rtl/spi.gtkwave b/rtl/spi.gtkwave
new file mode 100644
index 0000000..9ed44a7
--- /dev/null
+++ b/rtl/spi.gtkwave
@@ -0,0 +1,161 @@
+[*]
+[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
+[*] Fri Nov 16 17:18:13 2018
+[*]
+[dumpfile] "/home/matt/work/fpga/mlaccel/rtl/sspi/testbench.vcd"
+[dumpfile_mtime] "Fri Nov 16 17:17:10 2018"
+[dumpfile_size] 1547642
+[savefile] "/home/matt/work/fpga/mlaccel/rtl/sspi/spi.gtkwave"
+[timestart] 103746
+[size] 1917 1020
+[pos] -1 -1
+*-8.000000 104454 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] testbench.
+[treeopen] testbench.uut.
+[treeopen] testbench.uut.mem.
+[treeopen] testbench.uut.mem.ram[0].
+[sst_width] 253
+[signals_width] 492
+[sst_expanded] 1
+[sst_vpaned_height] 306
+@28
+testbench.clock
+@2024
+^1 /home/matt/work/fpga/mlaccel/rtl/sspi/../../../../../../../tmp/../home/matt/work/fpga/mlaccel/rtl/sspi/../../../../../../../tmp/../home/matt/work/fpga/mlaccel/rtl/sspi/state_filter.txt
+testbench.uut.state[5:0]
+@22
+testbench.uut.buffer_ptr[10:0]
+testbench.uut.dout_data[7:0]
+@8024
+testbench.cursor
+@28
+testbench.uut.reset
+testbench.uut.spi.spi_csb_di
+testbench.spi_clk
+@22
+testbench.uut.dout_data[7:0]
+@28
+testbench.uut.din_start
+testbench.uut.spi.di_start
+testbench.uut.din_valid
+testbench.uut.spi_active
+@22
+testbench.uut.din_data[7:0]
+@29
+testbench.xfer_wait_start
+@28
+testbench.xfer_read_start
+@c00022
+testbench.xfer[7:0]
+@28
+(0)testbench.xfer[7:0]
+(1)testbench.xfer[7:0]
+(2)testbench.xfer[7:0]
+(3)testbench.xfer[7:0]
+(4)testbench.xfer[7:0]
+(5)testbench.xfer[7:0]
+(6)testbench.xfer[7:0]
+(7)testbench.xfer[7:0]
+@1401200
+-group_end
+@28
+testbench.spi_mosi_reg
+testbench.uut.spi.spi_csb_di
+testbench.spi_miso
+@200
+-
+@28
+testbench.uut.dout_valid
+testbench.uut.dout_ready
+testbench.uut.spi.dout_busy
+@c00024
+testbench.uut.spi.do_data[7:0]
+@28
+(0)testbench.uut.spi.do_data[7:0]
+(1)testbench.uut.spi.do_data[7:0]
+(2)testbench.uut.spi.do_data[7:0]
+(3)testbench.uut.spi.do_data[7:0]
+(4)testbench.uut.spi.do_data[7:0]
+(5)testbench.uut.spi.do_data[7:0]
+(6)testbench.uut.spi.do_data[7:0]
+(7)testbench.uut.spi.do_data[7:0]
+@1401200
+-group_end
+@c00024
+testbench.uut.spi.do_bit[2:0]
+@28
+(0)testbench.uut.spi.do_bit[2:0]
+(1)testbench.uut.spi.do_bit[2:0]
+(2)testbench.uut.spi.do_bit[2:0]
+@1401200
+-group_end
+@28
+testbench.uut.spi.spi_miso
+@200
+-
+@c00022
+testbench.uut.spi.din_data[7:0]
+@28
+(0)testbench.uut.spi.din_data[7:0]
+(1)testbench.uut.spi.din_data[7:0]
+(2)testbench.uut.spi.din_data[7:0]
+(3)testbench.uut.spi.din_data[7:0]
+(4)testbench.uut.spi.din_data[7:0]
+(5)testbench.uut.spi.din_data[7:0]
+(6)testbench.uut.spi.din_data[7:0]
+(7)testbench.uut.spi.din_data[7:0]
+@1401200
+-group_end
+@24
+testbench.uut.spi.di_bit[2:0]
+@c00028
+testbench.uut.spi.di_data[7:0]
+@28
+(0)testbench.uut.spi.di_data[7:0]
+(1)testbench.uut.spi.di_data[7:0]
+(2)testbench.uut.spi.di_data[7:0]
+(3)testbench.uut.spi.di_data[7:0]
+(4)testbench.uut.spi.di_data[7:0]
+(5)testbench.uut.spi.di_data[7:0]
+(6)testbench.uut.spi.di_data[7:0]
+(7)testbench.uut.spi.di_data[7:0]
+@1401200
+-group_end
+@28
+testbench.uut.spi_clk
+testbench.uut.spi.spi_mosi
+@200
+-
+@28
+testbench.uut.spi.spi_clk_di
+testbench.uut.spi.glitch_guard_clock_q0
+testbench.uut.spi.glitch_guard_negedge
+testbench.uut.spi.glitch_guard_posedge
+testbench.uut.spi.clk_q1
+testbench.uut.spi.clk_q2
+@200
+-
+@24
+testbench.uut.spi.di_bit[2:0]
+@22
+testbench.uut.spi.glitch_guard_di_bit_q0[3:0]
+testbench.uut.spi.glitch_guard_di_bit[3:0]
+@200
+-
+@24
+testbench.uut.spi.do_bit[2:0]
+@22
+testbench.uut.spi.glitch_guard_do_bit_q0[3:0]
+testbench.uut.spi.glitch_guard_do_bit[3:0]
+@200
+-
+@22
+testbench.uut.mem.addr0[13:0]
+testbench.uut.mem.addr[15:0]
+testbench.uut.mem.rdata[63:0]
+testbench.uut.mem.wdata[63:0]
+testbench.uut.state[5:0]
+testbench.uut.buffer_ptr[10:0]
+testbench.uut.mem.wen[7:0]
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/rtl/spi.sby b/rtl/spi.sby
new file mode 100644
index 0000000..4d2d555
--- /dev/null
+++ b/rtl/spi.sby
@@ -0,0 +1,14 @@
+[options]
+mode prove
+multiclock on
+depth 20
+
+[engines]
+smtbmc 
+
+[script]
+read_verilog -formal spi_client.v
+prep -top spi_client
+
+[files]
+spi_client.v
diff --git a/rtl/spi_client.v b/rtl/spi_client.v
new file mode 100644
index 0000000..345c652
--- /dev/null
+++ b/rtl/spi_client.v
@@ -0,0 +1,288 @@
+`default_nettype none
+module spi_client (
+    input               i_clock,
+    input               i_reset,
+    output              o_active,           // high whenever chip selected
+
+    input               i_spi_clk,          // spi clock
+    input               i_spi_cs_n,         // spi chip select, low to select
+
+    output reg          o_miso,             // output to master
+    input               i_mosi,             // input from master
+   
+    output reg          o_data_in_valid,    // data from master is ready to read on the data_in_data reg
+    output reg          o_data_in_start,    // high for first byte received after cs goes low
+    output reg [7:0]    o_data_in_data,     // data register from master
+
+    input               i_data_out_valid,   // data in the input data bus is valid to read
+    output reg          o_data_out_ready,   // data has been registered
+    input [7:0]         i_data_out_data     // input data to send to the master
+);
+
+
+    assign o_active = !i_spi_cs_n;
+
+    // data coming from master goes here
+    reg [2:0] in_bit = 0;
+    reg [7:0] data_in = 0;
+
+    // data to send goes here
+    reg [2:0] out_bit = 0;
+    reg [7:0] data_out = 0;
+    // copy of data_out for the spi_clock domain
+    reg [7:0] data_out_spi = 0;
+    reg [7:0] data_in_spi = 0;
+
+
+    reg first_byte = 0;
+    reg start_status = 0; // registers data_in_start
+
+
+    always @(posedge i_spi_clk, posedge i_spi_cs_n) begin
+        if(i_spi_cs_n) begin                  // reset state
+            in_bit <= 0;
+            first_byte <= 1;
+        end else begin                      // receiving data
+            data_in[3'd7-in_bit] <= i_mosi;
+            in_bit <= in_bit + 1;
+            if(in_bit == 7) begin
+                data_in_spi <= { data_in[7:1], i_mosi };
+                first_byte <= 0;
+            end
+        end
+    end
+
+    always @(negedge i_spi_clk, posedge i_spi_cs_n) begin
+        if(i_spi_cs_n) begin                  // reset state
+            out_bit <= 0;
+        end else begin
+            if(out_bit == 7)                  // get a local copy of the data to send out - guaranteed stable
+                data_out_spi <= data_out;
+            o_miso <= data_out_spi[3'd7-out_bit];
+            out_bit <= out_bit + 1;
+        end
+    end
+
+    localparam DATA_IN_WAIT = 0;
+    localparam DATA_IN_RX = 1;
+    localparam DATA_IN_READY = 2;
+    localparam DATA_IN_ENDSTATE = 3;
+    reg [$clog2(DATA_IN_ENDSTATE)-1:0] data_in_state = DATA_IN_WAIT;
+
+    localparam DATA_OUT_WAIT = 0;
+    localparam DATA_OUT_TX = 1;
+    localparam DATA_OUT_ENDSTATE = 2;
+    reg [$clog2(DATA_OUT_ENDSTATE)-1:0] data_out_state = DATA_OUT_WAIT;
+
+    // clock domain crossing with 2 flip flops and one for what happened one clock ago
+    reg out_bit_clock, out_bit_clock_past, out_bit_clock_pipe;
+    reg in_bit_clock, in_bit_clock_past, in_bit_clock_pipe;
+    reg fb_clock, fb_clock_past, fb_clock_pipe;
+
+    initial begin
+        { out_bit_clock_past, out_bit_clock, out_bit_clock_pipe } = 0;
+        { in_bit_clock_past, in_bit_clock, in_bit_clock_pipe } = 0;
+        { fb_clock, fb_clock_past, fb_clock_pipe } = 3'b111;
+    end
+
+    always @(posedge i_clock) begin
+        { out_bit_clock_past, out_bit_clock, out_bit_clock_pipe } <= { out_bit_clock, out_bit_clock_pipe, out_bit[2] };
+        { in_bit_clock_past, in_bit_clock, in_bit_clock_pipe } <= { in_bit_clock, in_bit_clock_pipe, in_bit == 7 };
+        { fb_clock_past, fb_clock, fb_clock_pipe } <= { fb_clock, fb_clock_pipe, first_byte };
+    end
+
+    initial begin
+        data_in_state <= DATA_IN_WAIT;
+        data_out_state <= DATA_OUT_WAIT;
+        o_data_in_start <= 0;
+        o_data_out_ready <= 0;
+        start_status <= 0;
+    end
+
+    always @(posedge i_clock) begin
+        if(i_reset) begin
+            data_in_state <= DATA_IN_WAIT;
+            data_out_state <= DATA_OUT_WAIT;
+            o_data_in_start <= 0;
+            o_data_out_ready <= 0;
+            start_status <= 0;
+        end
+        else begin
+
+            case(data_in_state)
+                DATA_IN_WAIT: begin
+                    start_status <= fb_clock;
+                    o_data_in_valid <= 0;
+                    if(in_bit_clock == 1)
+                        data_in_state <= DATA_IN_RX;
+                end
+                DATA_IN_RX: begin
+                    if(in_bit_clock == 0)
+                        data_in_state <= DATA_IN_READY;
+                end 
+                DATA_IN_READY: begin
+                    o_data_in_valid <= 1;
+                    o_data_in_start <= start_status;
+                    o_data_in_data <= data_in_spi;
+                    data_in_state <= DATA_IN_WAIT;
+                end
+            endcase
+
+            case(data_out_state)
+                DATA_OUT_WAIT: begin
+                    if({out_bit_clock, out_bit_clock_past} == 2'b10)
+                        if(i_data_out_valid) begin
+                            data_out <= i_data_out_data;
+                            o_data_out_ready <= 1;
+                            data_out_state <= DATA_OUT_TX;
+                        end
+                end
+                DATA_OUT_TX: begin
+                    o_data_out_ready <= 0;
+                    if({out_bit_clock, out_bit_clock_past} == 2'b01)
+                        data_out_state <= DATA_OUT_WAIT;
+                end
+
+            endcase
+        end
+    end
+
+`ifdef FORMAL
+    reg [3:0] f_clk_counter;
+    initial f_clk_counter = 0;
+
+    // ASSUMPTIONS
+
+    initial assume(i_reset);
+    initial assume(i_spi_cs_n);
+    
+    // past valid signal
+    reg f_past_valid = 0;
+    always @($global_clock)
+        f_past_valid <= 1'b1;
+
+    // stop reset from happening after start
+    always @($global_clock)
+        if(f_past_valid)
+            assume(i_reset == 0);
+
+    // fix sys clock
+    wire [7:0] f_sys_step = 8'h40;
+    reg [7:0] f_sys_counter;
+    reg [7:0] f_spi_counter;
+
+    // system clock
+    always @($global_clock) begin
+        f_sys_counter <= f_sys_counter + f_sys_step;
+        assume ( i_clock == f_sys_counter [7]);
+    end
+
+    // spi clock
+    // allow spi clock to be around 1/4 sys clock
+    (* anyconst *) wire [7:0] f_spi_step;
+    always @(*)
+        assume ((f_spi_step > 8'h05) && (f_spi_step <= 8'h15));
+
+    // spi clock if spi_cs_n
+    always @($global_clock) begin
+        f_spi_counter <= f_spi_counter + f_spi_step;
+        assume ( i_spi_cs_n || i_spi_clk == f_spi_counter [7]);
+    end
+
+    // inputs only can change on system clock
+    always @($global_clock) 
+        if(f_past_valid && !$rose(i_clock)) begin
+            assume($stable(i_data_out_valid));
+            assume($stable(i_data_out_data));
+            assume($stable(i_reset));
+        end
+
+    // SPI assumptions
+    // mosi is stable as spi clock rises
+    always @($global_clock) 
+        if(f_past_valid && i_spi_clk) begin
+            assume($stable(i_mosi));
+        end
+    
+    // if no clock, no chip select
+    always @(*)
+        if(!i_spi_clk)
+            assume(!i_spi_cs_n);
+
+    // no chip select, no clock
+    always @($global_clock)
+        if(f_past_valid)
+            if($rose(i_spi_cs_n) || $fell(i_spi_cs_n))
+                assume($stable(i_spi_clk) && i_spi_clk);
+
+    // controller behaves by keeping valid line high and not changing data until we are ready
+    always @(posedge i_clock)
+        if(f_past_valid)
+            if($past(i_data_out_valid) && $past(!o_data_out_ready))
+                assume($stable(i_data_out_data) && i_data_out_valid);
+
+    // ensure chip select is held long enough to be effective
+    reg [2:0] chip_select_count = 0;
+    always @($global_clock) 
+        if(i_spi_cs_n == 1 && chip_select_count < 7)
+            chip_select_count <= chip_select_count + 1;
+        else if(i_spi_cs_n == 0)
+            chip_select_count <= 0;
+
+    always @($global_clock)
+        if(f_past_valid)
+            if(chip_select_count < 3)
+                assume(!$fell(i_spi_cs_n));
+
+
+    // ASSERTIONS
+
+
+    // assert everything is zeroed on the reset signal
+    always @($global_clock)
+        if (f_past_valid)
+            if ($past(i_reset) && $rose(i_clock)) begin
+                assert(data_out_state == DATA_OUT_WAIT);
+                assert(data_in_state == DATA_IN_WAIT);
+                assert(o_data_in_start == 0);
+            end
+
+    // spi counters are reset on cs_n
+    always @($global_clock)
+        if (f_past_valid)
+            if ($past(i_spi_cs_n) && $stable(i_spi_clk)) begin
+                assert(in_bit == 0);
+                assert(out_bit == 0);
+                assert(first_byte == 1);
+            end
+
+    // counters increase
+    always @($global_clock) begin
+        if (f_past_valid) begin
+            if(!i_spi_cs_n && $rose(i_spi_clk))
+                assert(in_bit != $past(in_bit));
+            if(!i_spi_cs_n && $fell(i_spi_clk))
+                assert(out_bit != $past(out_bit));
+        end
+    end
+    
+    // state machines: so simple just make sure they stay bounded
+    always @($global_clock) begin
+        assert(data_out_state < DATA_OUT_ENDSTATE);
+        assert(data_in_state < DATA_IN_ENDSTATE);
+    end
+
+    // CDC ensure data_out doesn't change while it's being copied to data_out_spi
+    always @($global_clock)
+        if(f_past_valid)
+            if(out_bit == 6 || out_bit == 7)
+                assert($stable(data_out));
+
+    // CDC: capturing data from mosi and putting into controller's clock domain
+    always @($global_clock) 
+        if(f_past_valid)
+            if($rose(i_clock) && data_in_state == DATA_IN_READY)
+                assert($stable(data_in_spi));
+
+`endif
+endmodule
diff --git a/rtl/spi_data_in_filter.txt b/rtl/spi_data_in_filter.txt
new file mode 100644
index 0000000..d3c8846
--- /dev/null
+++ b/rtl/spi_data_in_filter.txt
@@ -0,0 +1,3 @@
+0 = WAIT
+1 = RX
+2 = READY
diff --git a/rtl/spi_data_out_filter.txt b/rtl/spi_data_out_filter.txt
new file mode 100644
index 0000000..a67ef83
--- /dev/null
+++ b/rtl/spi_data_out_filter.txt
@@ -0,0 +1,2 @@
+0 = WAIT
+1 = TX
diff --git a/rtl/spi_formal.gtkw b/rtl/spi_formal.gtkw
new file mode 100644
index 0000000..0665db5
--- /dev/null
+++ b/rtl/spi_formal.gtkw
@@ -0,0 +1,54 @@
+[*]
+[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
+[*] Mon Nov 19 16:36:01 2018
+[*]
+[dumpfile] "/home/matt/work/fpga/mlaccel/rtl/spi/engine_0/trace_induct.vcd"
+[dumpfile_mtime] "Mon Nov 19 16:31:51 2018"
+[dumpfile_size] 8257
+[savefile] "/home/matt/work/fpga/mlaccel/rtl/spi_formal.gtkw"
+[timestart] 0
+[size] 1774 1134
+[pos] -295 114
+*-6.258204 190 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 253
+[signals_width] 519
+[sst_expanded] 1
+[sst_vpaned_height] 332
+@c00200
+-spi_client.f_clk_counter
+@1401200
+-group_end
+@28
+spi_client.i_clock
+spi_client.i_spi_clk
+spi_client.i_mosi
+spi_client.i_reset
+spi_client.i_spi_cs_n
+@24
+spi_client.chip_select_count[2:0]
+@200
+-
+@22
+spi_client.i_data_out_data[7:0]
+@28
+spi_client.i_data_out_valid
+@24
+spi_client.out_bit[2:0]
+@22
+spi_client.data_out[7:0]
+@28
+spi_client.data_out_state
+@200
+-
+@23
+spi_client.data_in[7:0]
+@24
+spi_client.in_bit[2:0]
+@28
+spi_client.data_in_state[1:0]
+spi_client.o_data_in_start
+spi_client.i_spi_cs_n
+spi_client.spi_cs_n_clock_pipe
+spi_client.spi_cs_n_clock
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/rtl/spitest.gtkw b/rtl/spitest.gtkw
new file mode 100644
index 0000000..c8c77d3
--- /dev/null
+++ b/rtl/spitest.gtkw
@@ -0,0 +1,102 @@
+[*]
+[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
+[*] Wed Nov 21 17:06:54 2018
+[*]
+[dumpfile] "/home/matt/work/fpga/mlaccel/rtl/testbench.vcd"
+[dumpfile_mtime] "Wed Nov 21 12:09:29 2018"
+[dumpfile_size] 587223476
+[savefile] "/home/matt/work/fpga/mlaccel/rtl/spitest.gtkw"
+[timestart] 0
+[size] 2512 1573
+[pos] -2513 -1
+*-18.000000 903682 1015310 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] testbench.
+[treeopen] testbench.uut.
+[treeopen] testbench.uut.mem.ram[0].
+[sst_width] 303
+[signals_width] 456
+[sst_expanded] 1
+[sst_vpaned_height] 500
+@28
+testbench.uut.reset
+@8022
+testbench.cursor
+@24
+testbench.len
+@8022
+testbench.i
+@28
+testbench.uut.clock
+@22
+testbench.xfer_send_byte.data[7:0]
+@c00022
+testbench.xfer[7:0]
+@28
+(0)testbench.xfer[7:0]
+(1)testbench.xfer[7:0]
+(2)testbench.xfer[7:0]
+(3)testbench.xfer[7:0]
+(4)testbench.xfer[7:0]
+(5)testbench.xfer[7:0]
+(6)testbench.xfer[7:0]
+(7)testbench.xfer[7:0]
+@1401200
+-group_end
+@22
+testbench.uut.din_data[7:0]
+@28
+testbench.xfer_read_start
+@29
+testbench.xfer_wait_start
+@200
+-
+-
+@28
+testbench.uut.spi.i_spi_clk
+testbench.uut.spi.i_spi_cs_n
+testbench.uut.spi.i_mosi
+testbench.uut.spi.o_miso
+@200
+-
+@28
+testbench.uut.spi.o_active
+@200
+-
+@24
+testbench.uut.spi.in_bit[2:0]
+@22
+testbench.uut.spi.data_in[7:0]
+testbench.uut.spi.data_in_spi[7:0]
+testbench.uut.spi.o_data_in_data[7:0]
+@2022
+^1 /home/matt/work/fpga/mlaccel/rtl/../../../../../../tmp/../home/matt/work/fpga/mlaccel/rtl/spi_data_in_filter.txt
+testbench.uut.spi.data_in_state[1:0]
+@200
+-
+@28
+testbench.uut.spi.o_data_in_start
+testbench.uut.spi.o_data_in_valid
+testbench.uut.spi.start_status
+testbench.uut.spi.in_bit_clock
+testbench.uut.spi.in_bit_clock_past
+@200
+-
+@2024
+^1 /home/matt/work/fpga/mlaccel/rtl/../../../../../../tmp/../home/matt/work/fpga/mlaccel/rtl/spi_data_in_filter.txt
+testbench.uut.spi.data_out_state
+@28
+testbench.uut.spi.i_data_out_valid
+testbench.uut.spi.o_data_out_ready
+@22
+testbench.uut.spi.i_data_out_data[7:0]
+testbench.uut.spi.data_out[7:0]
+@24
+testbench.uut.spi.out_bit[2:0]
+@22
+testbench.uut.spi.data_out_spi[7:0]
+@28
+testbench.uut.spi.out_bit_clock
+testbench.uut.spi.out_bit_clock_past
+testbench.uut.spi.o_miso
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/rtl/spitest.gtkwave b/rtl/spitest.gtkwave
new file mode 100644
index 0000000..99cb1e8
--- /dev/null
+++ b/rtl/spitest.gtkwave
@@ -0,0 +1,57 @@
+[*]
+[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
+[*] Tue Nov 20 18:15:20 2018
+[*]
+[dumpfile] "/home/mattvenn/work/fpga/mlaccel/rtl/testbench.vcd"
+[dumpfile_mtime] "Tue Nov 20 18:08:14 2018"
+[dumpfile_size] 4888613
+[savefile] "/home/mattvenn/work/fpga/mlaccel/rtl/spitest.gtkwave"
+[timestart] 38200
+[size] 1393 754
+[pos] -1 -1
+*-11.000000 44420 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] testbench.
+[treeopen] testbench.uut.
+[sst_width] 263
+[signals_width] 252
+[sst_expanded] 1
+[sst_vpaned_height] 209
+@28
+testbench.clock
+@8022
+testbench.cursor[31:0]
+@22
+testbench.xfer[7:0]
+@28
+testbench.xfer_wait_start
+testbench.xfer_read_start
+@200
+-
+@28
+testbench.uut.spi.i_spi_clk
+testbench.uut.spi.i_spi_cs_n
+@200
+-mosi
+@28
+testbench.uut.spi.i_mosi
+@22
+testbench.uut.spi.o_data_in_data[7:0]
+@28
+testbench.uut.spi.o_data_in_start
+testbench.uut.spi.o_data_in_valid
+@22
+testbench.uut.din_data[7:0]
+@200
+-
+-miso
+@28
+testbench.uut.spi.o_miso
+@22
+testbench.uut.spi.i_data_out_data[7:0]
+@23
+testbench.uut.dout_data[7:0]
+@28
+testbench.uut.spi.i_data_out_valid
+testbench.uut.spi.o_data_out_ready
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/rtl/spitest_simple.gtkw b/rtl/spitest_simple.gtkw
new file mode 100644
index 0000000..3571862
--- /dev/null
+++ b/rtl/spitest_simple.gtkw
@@ -0,0 +1,69 @@
+[*]
+[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
+[*] Mon Nov 19 17:11:30 2018
+[*]
+[dumpfile] "/home/matt/work/fpga/mlaccel/rtl/testbench.vcd"
+[dumpfile_mtime] "Mon Nov 19 17:08:52 2018"
+[dumpfile_size] 149967
+[savefile] "/home/matt/work/fpga/mlaccel/rtl/spitest.gtkw"
+[timestart] 10499
+[size] 1649 1029
+[pos] 317 470
+*-10.000000 13880 1015310 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] testbench.
+[treeopen] testbench.uut.
+[treeopen] testbench.uut.mem.ram[0].
+[sst_width] 303
+[signals_width] 456
+[sst_expanded] 1
+[sst_vpaned_height] 309
+@28
+testbench.uut.reset
+@8022
+testbench.cursor
+@28
+testbench.uut.clock
+@22
+testbench.xfer_send_byte.data[7:0]
+@c00022
+testbench.xfer[7:0]
+@28
+(0)testbench.xfer[7:0]
+(1)testbench.xfer[7:0]
+(2)testbench.xfer[7:0]
+(3)testbench.xfer[7:0]
+(4)testbench.xfer[7:0]
+(5)testbench.xfer[7:0]
+(6)testbench.xfer[7:0]
+(7)testbench.xfer[7:0]
+@1401200
+-group_end
+@200
+-
+-
+@28
+testbench.uut.spi.i_spi_clk
+testbench.uut.spi.i_spi_cs_n
+testbench.uut.spi.i_mosi
+testbench.uut.spi.o_miso
+@200
+-
+@28
+testbench.uut.spi.o_active
+@200
+-
+@28
+testbench.uut.spi.in_bit[2:0]
+@22
+testbench.uut.spi.data_in[7:0]
+testbench.uut.spi.data_in_spi[7:0]
+@200
+-
+@28
+testbench.uut.spi.o_data_in_start
+@29
+testbench.uut.spi.o_data_out_ready
+@200
+-
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/rtl/state_filter.txt b/rtl/state_filter.txt
new file mode 100644
index 0000000..7d9ddfa
--- /dev/null
+++ b/rtl/state_filter.txt
@@ -0,0 +1,14 @@
+0 = halt 
+1 = status
+2 = wbuf
+3 = rbuf
+4 = wmem0
+5 = wmem1
+6 = wmem2
+7 = wmem3
+8 = rmem0
+9 = rmem1
+10 = rmem2
+11 = rmem3
+12 = run0
+13 = run1
diff --git a/rtl/testbench.v b/rtl/testbench.v
index def924b..72b5d7d 100644
--- a/rtl/testbench.v
+++ b/rtl/testbench.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*
  *  Copyright (C) 2018  Clifford Wolf <clifford@symbioticeda.com>
  *
@@ -17,6 +18,7 @@
 
 module testbench;
 	reg clock;
+    localparam spi_clock_period = 17;
 
 	initial begin
 		$dumpfile("testbench.vcd");
@@ -26,90 +28,85 @@ module testbench;
 		forever #5 clock = ~clock;
 	end
 
-	reg qpi_csb;
-	reg qpi_clk;
+	reg spi_csb;
+	reg spi_clk;
 
-	reg qpi_io0_reg;
-	reg qpi_io1_reg;
-	reg qpi_io2_reg;
-	reg qpi_io3_reg;
+	reg spi_mosi_reg = 0;
+	reg spi_miso_reg = 0;
+    reg xfer_read_start = 0;
+    reg xfer_wait_start = 0;
 
-	wire qpi_io0 = qpi_io0_reg;
-	wire qpi_io1 = qpi_io1_reg;
-	wire qpi_io2 = qpi_io2_reg;
-	wire qpi_io3 = qpi_io3_reg;
+    wire spi_mosi = spi_mosi_reg;
+	wire spi_miso = spi_miso_reg;
 
-	wire qpi_rdy;
-	wire qpi_err;
+	wire spi_rdy;
+	wire spi_err;
 
 	mlaccel_top uut (
 		.clock   (clock  ),
-		.qpi_csb (qpi_csb),
-		.qpi_clk (qpi_clk),
-		.qpi_io0 (qpi_io0),
-		.qpi_io1 (qpi_io1),
-		.qpi_io2 (qpi_io2),
-		.qpi_io3 (qpi_io3),
-		.qpi_rdy (qpi_rdy),
-		.qpi_err (qpi_err)
+		.spi_csb (spi_csb),
+		.spi_clk (spi_clk),
+		.spi_miso (spi_miso),
+    	.spi_mosi (spi_mosi)
 	);
 
 	reg [7:0] xfer;
 
 	task xfer_posedge;
 		begin
-			if ($random & 15) begin
-				#17;
-				qpi_clk = 1;
-			end else begin
-				#17;
-				qpi_clk = 1;
-				#1;
-				qpi_clk = 0;
-				#1;
-				qpi_clk = 1;
-			end
+				#spi_clock_period;
+				spi_clk = 1;
 		end
 	endtask
 
 	task xfer_negedge;
 		begin
-			if ($random & 15) begin
-				#17;
-				qpi_clk = 0;
-			end else begin
-				#17;
-				qpi_clk = 0;
-				#1;
-				qpi_clk = 1;
-				#1;
-				qpi_clk = 0;
-			end
+				#spi_clock_period;
+				spi_clk = 0;
 		end
 	endtask
 
 	task xfer_start;
 		begin
-			#17;
-			qpi_csb = 0;
+			#spi_clock_period;
+			spi_csb = 0;
 		end
 	endtask
 
 	task xfer_send;
 		begin
 			xfer_negedge;
-			qpi_io0_reg = xfer[4];
-			qpi_io1_reg = xfer[5];
-			qpi_io2_reg = xfer[6];
-			qpi_io3_reg = xfer[7];
+			spi_mosi_reg = xfer[7];
+			xfer_posedge;
+
+			xfer_negedge;
+			spi_mosi_reg = xfer[6];
+			xfer_posedge;
+
+			xfer_negedge;
+			spi_mosi_reg = xfer[5];
+			xfer_posedge;
+            
+			xfer_negedge;
+			spi_mosi_reg = xfer[4];
+			xfer_posedge;
+
+			xfer_negedge;
+			spi_mosi_reg = xfer[3];
 			xfer_posedge;
 
 			xfer_negedge;
-			qpi_io0_reg = xfer[0];
-			qpi_io1_reg = xfer[1];
-			qpi_io2_reg = xfer[2];
-			qpi_io3_reg = xfer[3];
+			spi_mosi_reg = xfer[2];
 			xfer_posedge;
+
+			xfer_negedge;
+			spi_mosi_reg = xfer[1];
+			xfer_posedge;
+
+			xfer_negedge;
+			spi_mosi_reg = xfer[0];
+			xfer_posedge;
+
 		end
 	endtask
 
@@ -145,62 +142,92 @@ module testbench;
 		end
 	endtask
 
+    // null byte
 	task xfer_wait;
 		begin
+
+            xfer_wait_start = 1;
+			xfer_negedge;
+			spi_miso_reg = 1'bz;
+			xfer_posedge;
+
+			xfer_negedge;
+			xfer_posedge;
+
+			xfer_negedge;
+			xfer_posedge;
+
+			xfer_negedge;
+			xfer_posedge;
+
+			xfer_negedge;
+			xfer_posedge;
+
 			xfer_negedge;
-			qpi_io0_reg = 1'bz;
-			qpi_io1_reg = 1'bz;
-			qpi_io2_reg = 1'bz;
-			qpi_io3_reg = 1'bz;
 			xfer_posedge;
 
 			xfer_negedge;
 			xfer_posedge;
+
+			xfer_negedge;
+			xfer_posedge;
+
+            xfer_wait_start = 0;
+
 		end
 	endtask
 
 	task xfer_recv;
 		begin
+            xfer_read_start = 1;
+
 			xfer_negedge;
-			qpi_io0_reg = 1'bz;
-			qpi_io1_reg = 1'bz;
-			qpi_io2_reg = 1'bz;
-			qpi_io3_reg = 1'bz;
-			xfer_posedge;
+            xfer_posedge;
+			xfer[7] = spi_miso;
 
-			xfer[4] = qpi_io0;
-			xfer[5] = qpi_io1;
-			xfer[6] = qpi_io2;
-			xfer[7] = qpi_io3;
+            xfer_read_start = 0;
 
 			xfer_negedge;
-			xfer_posedge;
+            xfer_posedge;
+			xfer[6] = spi_miso;
+
+			xfer_negedge;
+            xfer_posedge;
+			xfer[5] = spi_miso;
+
+			xfer_negedge;
+            xfer_posedge;
+			xfer[4] = spi_miso;
+
+			xfer_negedge;
+            xfer_posedge;
+			xfer[3] = spi_miso;
+
+			xfer_negedge;
+            xfer_posedge;
+			xfer[2] = spi_miso;
+
+			xfer_negedge;
+            xfer_posedge;
+			xfer[1] = spi_miso;
+
+			xfer_negedge;
+            xfer_posedge;
+			xfer[0] = spi_miso;
 
-			xfer[0] = qpi_io0;
-			xfer[1] = qpi_io1;
-			xfer[2] = qpi_io2;
-			xfer[3] = qpi_io3;
 		end
 	endtask
 
 	task xfer_stop;
 		begin
-			if ($random & 3) begin
-				xfer_negedge;
-			end else begin
-				#17;
-			end
+				#spi_clock_period;
 
-			qpi_io0_reg = 1'bz;
-			qpi_io1_reg = 1'bz;
-			qpi_io2_reg = 1'bz;
-			qpi_io3_reg = 1'bz;
 			xfer = 'bx;
 
-			#17;
-			qpi_csb = 1;
-			#17;
-			qpi_clk = 1;
+			#spi_clock_period;
+			spi_csb = 1;
+			#spi_clock_period;
+			spi_clk = 1;
 		end
 	endtask
 
diff --git a/rtl/testbench_simple.v b/rtl/testbench_simple.v
new file mode 100644
index 0000000..c434305
--- /dev/null
+++ b/rtl/testbench_simple.v
@@ -0,0 +1,328 @@
+`default_nettype none
+/*
+ *  Copyright (C) 2018  Clifford Wolf <clifford@symbioticeda.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+module testbench;
+	reg clock;
+    localparam spi_clock_period = 17;
+    localparam no_glitch = 1;
+    localparam num_tests = 64;
+
+	initial begin
+		$dumpfile("testbench.vcd");
+		$dumpvars(0, testbench);
+
+		#5 clock = 0;
+		forever #5 clock = ~clock;
+	end
+
+	reg spi_csb;
+	reg spi_clk;
+
+	reg spi_mosi_reg = 0;
+	reg spi_miso_reg = 0;
+    reg xfer_read_start = 0;
+    reg xfer_wait_start = 0;
+
+    wire spi_mosi = spi_mosi_reg;
+	wire spi_miso = spi_miso_reg;
+
+	wire spi_rdy;
+	wire spi_err;
+
+	mlaccel_top uut (
+		.clock   (clock  ),
+		.spi_csb (spi_csb),
+		.spi_clk (spi_clk),
+		.spi_miso (spi_miso),
+    	.spi_mosi (spi_mosi)
+	);
+
+	reg [7:0] xfer;
+
+	task xfer_posedge;
+		begin
+			if ($random & 15 || no_glitch) begin
+				#spi_clock_period;
+				spi_clk = 1;
+			end else begin
+				#spi_clock_period;
+				spi_clk = 1;
+				#1;
+				spi_clk = 0;
+				#1;
+				spi_clk = 1;
+            end
+		end
+	endtask
+
+	task xfer_negedge;
+		begin
+			if ($random & 15 || no_glitch) begin
+				#spi_clock_period;
+				spi_clk = 0;
+			end else begin
+				#spi_clock_period;
+				spi_clk = 0;
+				#1;
+			    spi_clk = 1;
+				#1;
+				spi_clk = 0;
+			end
+		end
+	endtask
+
+	task xfer_start;
+		begin
+			#spi_clock_period;
+			spi_csb = 0;
+		end
+	endtask
+
+	task xfer_send;
+		begin
+			xfer_negedge;
+			spi_mosi_reg = xfer[7];
+			xfer_posedge;
+
+			xfer_negedge;
+			spi_mosi_reg = xfer[6];
+			xfer_posedge;
+
+			xfer_negedge;
+			spi_mosi_reg = xfer[5];
+			xfer_posedge;
+            
+			xfer_negedge;
+			spi_mosi_reg = xfer[4];
+			xfer_posedge;
+
+			xfer_negedge;
+			spi_mosi_reg = xfer[3];
+			xfer_posedge;
+
+			xfer_negedge;
+			spi_mosi_reg = xfer[2];
+			xfer_posedge;
+
+			xfer_negedge;
+			spi_mosi_reg = xfer[1];
+			xfer_posedge;
+
+			xfer_negedge;
+			spi_mosi_reg = xfer[0];
+			xfer_posedge;
+
+		end
+	endtask
+
+	task xfer_send_byte;
+		input [7:0] data;
+		begin
+			xfer = data;
+			xfer_send;
+		end
+	endtask
+
+	task xfer_send_hword;
+		input [15:0] data;
+		begin
+			xfer = data[7:0];
+			xfer_send;
+			xfer = data[15:8];
+			xfer_send;
+		end
+	endtask
+
+	task xfer_send_word;
+		input [31:0] data;
+		begin
+			xfer = data[7:0];
+			xfer_send;
+			xfer = data[15:8];
+			xfer_send;
+			xfer = data[23:16];
+			xfer_send;
+			xfer = data[31:24];
+			xfer_send;
+		end
+	endtask
+
+    // null byte
+	task xfer_wait;
+		begin
+
+            xfer_wait_start = 1;
+			xfer_negedge;
+			spi_miso_reg = 1'bz;
+			xfer_posedge;
+
+			xfer_negedge;
+			xfer_posedge;
+
+			xfer_negedge;
+			xfer_posedge;
+
+			xfer_negedge;
+			xfer_posedge;
+
+			xfer_negedge;
+			xfer_posedge;
+
+			xfer_negedge;
+			xfer_posedge;
+
+			xfer_negedge;
+			xfer_posedge;
+
+			xfer_negedge;
+			xfer_posedge;
+
+            xfer_wait_start = 0;
+
+		end
+	endtask
+
+	task xfer_recv;
+		begin
+            xfer_read_start = 1;
+
+			xfer_negedge;
+            xfer_posedge;
+			xfer[7] = spi_miso;
+
+            xfer_read_start = 0;
+
+			xfer_negedge;
+            xfer_posedge;
+			xfer[6] = spi_miso;
+
+			xfer_negedge;
+            xfer_posedge;
+			xfer[5] = spi_miso;
+
+			xfer_negedge;
+            xfer_posedge;
+			xfer[4] = spi_miso;
+
+			xfer_negedge;
+            xfer_posedge;
+			xfer[3] = spi_miso;
+
+			xfer_negedge;
+            xfer_posedge;
+			xfer[2] = spi_miso;
+
+			xfer_negedge;
+            xfer_posedge;
+			xfer[1] = spi_miso;
+
+			xfer_negedge;
+            xfer_posedge;
+			xfer[0] = spi_miso;
+
+		end
+	endtask
+
+	task xfer_stop;
+		begin
+			if ($random & 3 || no_glitch) begin
+				xfer_negedge;
+			end else begin
+				#spi_clock_period;
+			end
+
+			xfer = 'bx;
+
+			#spi_clock_period;
+			spi_csb = 1;
+			#spi_clock_period;
+			spi_clk = 1;
+		end
+	endtask
+
+	integer cursor, len, i;
+
+	initial begin
+		xfer_stop;
+
+		#200;
+
+		$display("sending bytes");
+		$fflush;
+
+        i= 0;
+        len = 1;
+		cursor = 0;
+		while (cursor < num_tests) begin
+                i = 0;
+				$display("  uploading %4d bytes from 0x%05x", len, cursor);
+				$fflush;
+
+				xfer_start;
+				xfer_send_byte(8'h 21);
+                xfer_send_byte(cursor);
+				xfer_stop;
+
+				xfer_start;
+				xfer_send_byte(8'h 23);
+				xfer_send_hword(cursor);
+				xfer_send_byte(len);
+				xfer_wait;
+				xfer_recv;
+
+				while (xfer != 8'h 00)
+					xfer_recv;
+				xfer_stop;
+
+				cursor = cursor + len;
+		end
+		$display("reading bytes");
+		$fflush;
+
+        len = 1;
+		cursor = 0;
+		while (cursor < num_tests) begin
+				$display("  downloading %4d bytes from 0x%05x", len, cursor);
+				$fflush;
+
+				xfer_start;
+				xfer_send_byte(8'h 24);
+				xfer_send_hword(cursor);
+				xfer_send_byte(len);
+				xfer_wait;
+				xfer_recv;
+				while (xfer != 8'h 00)
+					xfer_recv;
+				xfer_stop;
+
+				xfer_start;
+				xfer_send_byte(8'h 22);
+				xfer_wait;
+                xfer_recv;
+                if( xfer != cursor) begin
+                    $display("ERROR at %4d: expected 0x%02x, got 0x%02x", cursor, cursor, xfer);
+                end
+				xfer_stop;
+
+				cursor = cursor + len;
+		end
+
+
+		$finish;
+	end
+endmodule
diff --git a/rtl/top.v b/rtl/top.v
index 4ee47e1..571bb4f 100644
--- a/rtl/top.v
+++ b/rtl/top.v
@@ -1,31 +1,13 @@
-/*
- *  Copyright (C) 2018  Clifford Wolf <clifford@symbioticeda.com>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
+`default_nettype none
 module mlaccel_top (
 	input  clock,
 
-	input  qpi_csb,
-	input  qpi_clk,
-	inout  qpi_io0,
-	inout  qpi_io1,
-	inout  qpi_io2,
-	inout  qpi_io3,
-	output qpi_rdy,
-	output qpi_err
+	input  spi_csb,
+	input  spi_clk,
+	output spi_miso,
+	input  spi_mosi,
+	output spi_rdy,
+	output spi_err
 );
 	integer i;
 
@@ -89,73 +71,31 @@ module mlaccel_top (
 		reset <= !next_resetn;
 	end
 
+
 	/********** QPI Interface **********/
 
-	wire [3:0] qpi_io_oe;
-	wire [3:0] qpi_io_do;
-	wire [3:0] qpi_io_di;
-`ifdef RADIANT
-	BB_B qpi_io_buf [3:0] (
-		.B({qpi_io3, qpi_io2, qpi_io1, qpi_io0}),
-		.T_N(qpi_io_oe),
-		.I(qpi_io_do),
-		.O(qpi_io_di)
-	);
-`else
-	SB_IO #(
-		.PIN_TYPE(6'b 1010_01),
-		.PULLUP(1'b 0)
-	) qpi_io_buf [3:0] (
-		.PACKAGE_PIN({qpi_io3, qpi_io2, qpi_io1, qpi_io0}),
-		.OUTPUT_ENABLE(qpi_io_oe),
-		.D_OUT_0(qpi_io_do),
-		.D_IN_0(qpi_io_di)
-	);
-`endif
-	wire qpi_csb_di;
-	wire qpi_clk_di;
-`ifdef RADIANT
-	assign qpi_csb_di = qpi_csb;
-	assign qpi_clk_di = qpi_clk;
-`else
-	SB_IO #(
-		.PIN_TYPE(6'b 0000_01),
-		.PULLUP(1'b 1)
-	) qpi_csb_buf (
-		.PACKAGE_PIN(qpi_csb),
-		.D_IN_0(qpi_csb_di)
-	);
+	wire spi_active;
+    assign spi_rdy = 1;
+    assign spi_err = 1;
 
-	SB_IO #(
-		.PIN_TYPE(6'b 0000_01),
-		.PULLUP(1'b 0)
-	) qpi_clk_buf (
-		.PACKAGE_PIN(qpi_clk),
-		.D_IN_0(qpi_clk_di)
-	);
-`endif
-	wire qpi_active;
+	spi_client spi (
+		.i_clock      (clock     ),
+		.i_reset      (reset     ),
+		.o_active     (spi_active),
 
-	mlaccel_qpi qpi (
-		.clock      (clock     ),
-		.reset      (reset     ),
-		.active     (qpi_active),
-
-		.qpi_csb_di (qpi_csb_di),
-		.qpi_clk_di (qpi_clk_di),
-		.qpi_rdy_do (qpi_rdy   ),
-		.qpi_err_do (qpi_err   ),
-		.qpi_io_di  (qpi_io_di ),
-		.qpi_io_do  (qpi_io_do ),
-		.qpi_io_oe  (qpi_io_oe ),
-
-		.din_valid  (din_valid ),
-		.din_start  (din_start ),
-		.din_data   (din_data  ),
-
-		.dout_valid (dout_valid),
-		.dout_ready (dout_ready),
-		.dout_data  (dout_data )
+		.i_spi_cs_n (spi_csb),
+		.i_spi_clk  (spi_clk),
+
+		.o_miso   (spi_miso ),
+		.i_mosi   (spi_mosi ),
+
+		.o_data_in_valid  (din_valid ),
+		.o_data_in_start  (din_start ),
+		.o_data_in_data   (din_data  ),
+
+		.i_data_out_valid (dout_valid),
+		.o_data_out_ready (dout_ready),
+		.i_data_out_data  (dout_data )
 	);
 
 	/********** Cmd State Machine **********/
@@ -196,7 +136,7 @@ module mlaccel_top (
 		seq_start <= 0;
 		seq_stop <= 0;
 
-		if (!qpi_active || din_start) begin
+		if (!spi_active || din_start) begin
 			dout_valid <= 0;
 		end
 
@@ -512,173 +452,5 @@ module mlaccel_top (
 		.wdata (mem_wdata),
 		.rdata (mem_rdata)
 	);
-endmodule
-
-module mlaccel_qpi (
-	input            clock,
-	input            reset,
-	output           active,
-
-	input            qpi_csb_di,
-	input            qpi_clk_di,
-
-	output           qpi_rdy_do,
-	output           qpi_err_do,
-
-	input      [3:0] qpi_io_di,
-	output reg [3:0] qpi_io_do,
-	output reg [3:0] qpi_io_oe,
-
-	output reg       din_valid,
-	output reg       din_start,
-	output reg [7:0] din_data,
-
-	input            dout_valid,
-	output           dout_ready,
-	input      [7:0] dout_data
-);
-	assign qpi_rdy_do = 1;
-	assign qpi_err_do = 1;
-
-	reg [3:0] di_data;
-	reg di_toggle;
-	reg di_start;
-	reg di_stx;
-
-	reg [7:0] do_data;
-	reg [3:0] do_datax;
-	reg do_valid;
-	reg do_validx;
-	reg do_toggle;
-
-	reg glitch_guard_clock_q0;
-	reg glitch_guard_di_toggle_q0;
-	reg glitch_guard_do_toggle_q0;
-	reg glitch_guard_di_stx_q0;
-
-	reg glitch_guard_posedge;
-	reg glitch_guard_negedge;
-	reg glitch_guard_di_toggle;
-	reg glitch_guard_do_toggle;
-	reg glitch_guard_di_stx;
-
-	always @(negedge clock) begin
-		glitch_guard_clock_q0 <= qpi_clk_di;
-		glitch_guard_di_toggle_q0 <= di_toggle;
-		glitch_guard_do_toggle_q0 <= do_toggle;
-		glitch_guard_di_stx_q0 <= di_stx;
-	end
-
-	always @(posedge clock) begin
-		// protect against clock glitching: logic level of clock
-		// must have been low before posedge and high before negedge
-		glitch_guard_posedge <= !glitch_guard_clock_q0;
-		glitch_guard_negedge <= glitch_guard_clock_q0;
-
-		// delay some signals to protect against double clocking
-		glitch_guard_di_toggle <= glitch_guard_di_toggle_q0;
-		glitch_guard_do_toggle <= glitch_guard_do_toggle_q0;
-		glitch_guard_di_stx <= glitch_guard_di_stx_q0;
-	end
-
-	always @(posedge qpi_clk_di, posedge qpi_csb_di) begin
-		if (qpi_csb_di) begin
-			di_data <= 0;
-			di_toggle <= 1;
-			di_start <= 1;
-			di_stx <= 1;
-		end else begin
-			if (glitch_guard_posedge) begin
-				di_data <= qpi_io_di;
-				di_toggle <= !glitch_guard_di_toggle;
-				if (glitch_guard_di_toggle)
-					di_stx <= 0;
-				if (glitch_guard_di_toggle && !glitch_guard_di_stx)
-					di_start <= 0;
-			end
-		end
-	end
-
-	always @(negedge qpi_clk_di, posedge qpi_csb_di) begin
-		if (qpi_csb_di) begin
-			qpi_io_oe <= 0;
-			qpi_io_do <= 0;
-			do_toggle <= 0;
-			do_validx <= 0;
-			do_datax <= 0;
-		end else begin
-			if (glitch_guard_negedge) begin
-				if (di_start)
-					do_toggle <= 0;
-				else
-					do_toggle <= !glitch_guard_do_toggle;
-
-				if (glitch_guard_do_toggle) begin
-					qpi_io_oe <= {4{do_valid}};
-					qpi_io_do <= do_data[7:4];
-				end else begin
-					qpi_io_oe <= {4{do_validx}};
-					qpi_io_do <= do_datax;
-				end
-
-				do_validx <= do_valid;
-				do_datax <= do_data;
-			end
-		end
-	end
-
-	reg clk_q0, clk_q1, clk_q2;
-	reg do_toggle_q0, do_toggle_q1;
-	reg active_q0, active_q1;
-
-	always @(negedge clock) begin
-		clk_q0 <= qpi_clk_di;
-		do_toggle_q0 <= do_toggle;
-		active_q0 <= !qpi_csb_di;
-	end
-
-	always @(posedge clock) begin
-		clk_q1 <= clk_q0;
-		clk_q2 <= clk_q1;
-		do_toggle_q1 <= do_toggle_q0;
-		active_q1 <= active_q0;
-	end
 
-	reg dout_busy;
-	assign dout_ready = do_toggle_q1 && dout_valid && !dout_busy;
-	assign active = active_q1;
-
-	always @(posedge clock) begin
-		din_valid <= 0;
-		if (clk_q1 && !clk_q2) begin
-			if (!di_toggle) begin
-				din_data[7:4] <= di_data;
-			end else begin
-				din_valid <= 1;
-				din_start <= di_start;
-				din_data[3:0] <= di_data;
-			end
-		end
-		if (dout_valid && dout_ready) begin
-			do_valid <= 1;
-			do_data <= dout_data;
-			dout_busy <= 1;
-		end
-		if (!do_toggle_q1) begin
-			dout_busy <= 0;
-		end
-		if (!active) begin
-			do_valid <= 0;
-			do_data <= 0;
-			dout_busy <= 0;
-		end
-		if (reset) begin
-			do_valid <= 0;
-			do_data <= 0;
-			din_valid <= 0;
-			din_start <= 0;
-			din_data <= 0;
-			dout_busy <= 0;
-		end
-	end
 endmodule