From 40e6d917a42f46aec31ee58a868a0138d5a6e8af Mon Sep 17 00:00:00 2001
From: Joshua Leahy <jleahy@xtxmarkets.com>
Date: Wed, 18 Sep 2019 19:06:13 +0100
Subject: [PATCH 1/3] Handle nested ifdef in generate.py

This is required to properly handle the BEQ instruction with compressed
instructions disabled. Currently in this case invalid verilog output
is produced.
---
 monitor/generate.py | 75 ++++++++++++---------------------------------
 1 file changed, 20 insertions(+), 55 deletions(-)

diff --git a/monitor/generate.py b/monitor/generate.py
index c65003c..b9846da 100644
--- a/monitor/generate.py
+++ b/monitor/generate.py
@@ -590,77 +590,42 @@ def usage():
         insn_list.append(insn)
         replace_db.append((" rvfi_insn_%s " % insn, " %s_insn_%s " % (prefix, insn)))
 
+expected_flags = {
+    "RISCV_FORMAL_COMPRESSED": compressed,
+    "RISCV_FORMAL_ALIGNED_MEM": aligned,
+}
+
 def print_rewrite_file(filename):
     with open(filename) as f:
-        flag_compressed_ifdef = False
-        flag_compressed_ifndef = False
-        flag_aligned_ifdef = False
-        flag_aligned_ifndef = False
-        flag_ifdef = False
-        flag_ifndef = False
+        flag_stack = []
+        flags = {}
 
         for line in f:
-            if line.startswith("`ifdef RISCV_FORMAL_COMPRESSED"):
-                flag_compressed_ifdef = True
-                flag_compressed_ifndef = False
-                continue
-
-            if line.startswith("`ifndef RISCV_FORMAL_COMPRESSED"):
-                flag_compressed_ifdef = False
-                flag_compressed_ifndef = True
-                continue
-
-            if line.startswith("`ifdef RISCV_FORMAL_ALIGNED_MEM"):
-                flag_aligned_ifdef = True
-                flag_aligned_ifndef = False
-                continue
-
-            if line.startswith("`ifndef RISCV_FORMAL_ALIGNED_MEM"):
-                flag_aligned_ifdef = False
-                flag_aligned_ifndef = True
-                continue
-
             if line.startswith("`ifdef "):
-                flag_ifdef = True
-                flag_ifndef = False
+                flag_name = line.split()[1]
+                assert flag_name not in flags, (filename, flag_name, flags)
+                flag_stack.append(flag_name)
+                flags[flag_name] = True
                 continue
 
             if line.startswith("`ifndef "):
-                flag_ifdef = False
-                flag_ifndef = True
+                flag_name = line.split()[1]
+                assert flag_name not in flags
+                flag_stack.append(flag_name)
+                flags[flag_name] = False
                 continue
 
             if line.startswith("`else"):
-                flag_compressed_ifdef, flag_compressed_ifndef = flag_compressed_ifndef, flag_compressed_ifdef
-                flag_aligned_ifdef, flag_aligned_ifndef = flag_aligned_ifndef, flag_aligned_ifdef
-                flag_ifdef, flag_ifndef = flag_ifndef, flag_ifdef
+                flag_name = flag_stack[-1]
+                flags[flag_name] = not flags[flag_name]
                 continue
 
             if line.startswith("`endif"):
-                flag_compressed_ifdef = False
-                flag_compressed_ifndef = False
-                flag_aligned_ifdef = False
-                flag_aligned_ifndef = False
-                flag_ifdef = False
-                flag_ifndef = False
-                continue
-
-            if flag_compressed_ifdef and not compressed:
-                continue
-
-            if flag_compressed_ifndef and compressed:
-                continue
-
-            if flag_aligned_ifdef and not aligned:
-                continue
-
-            if flag_aligned_ifndef and aligned:
-                continue
-
-            if flag_ifdef and True:
+                flag_name = flag_stack.pop()
+                del flags[flag_name]
                 continue
 
-            if flag_ifndef and False:
+            if any(expected_flags.get(name, False) != val for name, val in flags.items()):
                 continue
 
             for a, b in replace_db:

From 3e2dac95fcf8cc07de669f38893166f67a496126 Mon Sep 17 00:00:00 2001
From: Joshua Leahy <jleahy@xtxmarkets.com>
Date: Wed, 18 Sep 2019 19:07:19 +0100
Subject: [PATCH 2/3] Prevent warning in icarus verilog with output of
 generate.py

This is unfortunate as it requires switching between wire/reg, but otherwise
icarus verilog complains that this always block has no sensitivity list.
---
 monitor/generate.py | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/monitor/generate.py b/monitor/generate.py
index b9846da..2273689 100644
--- a/monitor/generate.py
+++ b/monitor/generate.py
@@ -522,7 +522,10 @@ def usage():
         print("    output reg o%d_valid," % (chidx))
         print("    output reg [63:0] o%d_order," % (chidx))
         print("    output reg [%d:0] o%d_data," % (rob_data_width-1, chidx))
-    print("  output reg [15:0] errcode")
+    if robdepth == 0:
+        print("  output wire [15:0] errcode")
+    else:
+        print("  output reg [15:0] errcode")
     print(");")
 
     if robdepth == 0:
@@ -530,7 +533,7 @@ def usage():
             print("  always @* o%d_valid = i%d_valid;" % (chidx, chidx))
             print("  always @* o%d_order = i%d_order;" % (chidx, chidx))
             print("  always @* o%d_data = i%d_data;" % (chidx, chidx))
-        print("  always @* errcode = 0;")
+        print("  assign errcode = 0;")
 
     else:
         orderbits = ceil(log2(robdepth))

From d8289578d71acef3ce21c68f26bb88e66bceb096 Mon Sep 17 00:00:00 2001
From: Joshua Leahy <jleahy@xtxmarkets.com>
Date: Wed, 18 Sep 2019 19:08:11 +0100
Subject: [PATCH 3/3] Make generate.py executable within Git

This should save people one step when checking the repository out on Linux
---
 monitor/generate.py | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 mode change 100644 => 100755 monitor/generate.py

diff --git a/monitor/generate.py b/monitor/generate.py
old mode 100644
new mode 100755