From 0120f5862c7cf1f62d5d16067cbc56f16846e8cc Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sat, 25 Nov 2017 21:30:34 +0100 Subject: [PATCH 1/4] Pass imemcheck SpinalHDL 0.11.3 VexRiscv --- cores/VexRiscv/README.md | 11 +- cores/VexRiscv/VexRiscv.v | 2830 ++++++++++++++++------------------ cores/VexRiscv/imemcheck.sby | 21 + cores/VexRiscv/imemcheck.sv | 105 ++ 4 files changed, 1478 insertions(+), 1489 deletions(-) create mode 100644 cores/VexRiscv/imemcheck.sby create mode 100644 cores/VexRiscv/imemcheck.sv diff --git a/cores/VexRiscv/README.md b/cores/VexRiscv/README.md index 2933195..6e6341e 100644 --- a/cores/VexRiscv/README.md +++ b/cores/VexRiscv/README.md @@ -12,6 +12,9 @@ All standards checks are passing - Causality - Liveness +Other tests passing : +- Instruction Memory check + ### Quickstart guide: First install Yosys, SymbiYosys, and the solvers. See [here](http://symbiyosys.readthedocs.io/en/latest/quickstart.html#installing) @@ -34,9 +37,15 @@ python3 ../../checks/genchecks.py export test=insn_beq_ch0; rm -r checks/$test; make -C checks -j$(nproc) $test/PASS; python3 disasm.py checks/$test/engine_0/trace.vcd ``` + +Running the instruction memory check : + +``` +sby -f imemcheck.sby +``` + ### Todo: - Integrate others VexRiscv configurations into the framework -- Add Instruction Memcheck check - Add Data Memcheck check - Add Checking for equivalence of core with and without RVFI check - Add Complete check diff --git a/cores/VexRiscv/VexRiscv.v b/cores/VexRiscv/VexRiscv.v index e6468e0..8329845 100644 --- a/cores/VexRiscv/VexRiscv.v +++ b/cores/VexRiscv/VexRiscv.v @@ -1,122 +1,341 @@ -// Generator : SpinalHDL v0.10.15 git head : b2cc963be712aa10e43c07c8c2d261d3433a28ef -// Date : 06/11/2017, 22:40:17 +// Generator : SpinalHDL v0.11.3 git head : 4d8502333f4f7d6be245912fd85227ba7847abbd +// Date : 24/11/2017, 12:08:46 // Component : VexRiscv - -`define AluCtrlEnum_binary_sequancial_type [1:0] -`define AluCtrlEnum_binary_sequancial_ADD_SUB 'b00 -`define AluCtrlEnum_binary_sequancial_SLT_SLTU 'b01 -`define AluCtrlEnum_binary_sequancial_BITWISE 'b10 - -`define Src1CtrlEnum_binary_sequancial_type [1:0] -`define Src1CtrlEnum_binary_sequancial_RS 'b00 -`define Src1CtrlEnum_binary_sequancial_IMU 'b01 -`define Src1CtrlEnum_binary_sequancial_FOUR 'b10 -`define ShiftCtrlEnum_binary_sequancial_type [1:0] -`define ShiftCtrlEnum_binary_sequancial_DISABLE_1 'b00 -`define ShiftCtrlEnum_binary_sequancial_SLL_1 'b01 -`define ShiftCtrlEnum_binary_sequancial_SRL_1 'b10 -`define ShiftCtrlEnum_binary_sequancial_SRA_1 'b11 +`define BranchCtrlEnum_binary_sequancial_type [1:0] +`define BranchCtrlEnum_binary_sequancial_INC 2'b00 +`define BranchCtrlEnum_binary_sequancial_B 2'b01 +`define BranchCtrlEnum_binary_sequancial_JAL 2'b10 +`define BranchCtrlEnum_binary_sequancial_JALR 2'b11 `define Src2CtrlEnum_binary_sequancial_type [1:0] -`define Src2CtrlEnum_binary_sequancial_RS 'b00 -`define Src2CtrlEnum_binary_sequancial_IMI 'b01 -`define Src2CtrlEnum_binary_sequancial_IMS 'b10 -`define Src2CtrlEnum_binary_sequancial_PC 'b11 +`define Src2CtrlEnum_binary_sequancial_RS 2'b00 +`define Src2CtrlEnum_binary_sequancial_IMI 2'b01 +`define Src2CtrlEnum_binary_sequancial_IMS 2'b10 +`define Src2CtrlEnum_binary_sequancial_PC 2'b11 -`define BranchCtrlEnum_binary_sequancial_type [1:0] -`define BranchCtrlEnum_binary_sequancial_INC 'b00 -`define BranchCtrlEnum_binary_sequancial_B 'b01 -`define BranchCtrlEnum_binary_sequancial_JAL 'b10 -`define BranchCtrlEnum_binary_sequancial_JALR 'b11 +`define AluCtrlEnum_binary_sequancial_type [1:0] +`define AluCtrlEnum_binary_sequancial_ADD_SUB 2'b00 +`define AluCtrlEnum_binary_sequancial_SLT_SLTU 2'b01 +`define AluCtrlEnum_binary_sequancial_BITWISE 2'b10 `define AluBitwiseCtrlEnum_binary_sequancial_type [1:0] -`define AluBitwiseCtrlEnum_binary_sequancial_XOR_1 'b00 -`define AluBitwiseCtrlEnum_binary_sequancial_OR_1 'b01 -`define AluBitwiseCtrlEnum_binary_sequancial_AND_1 'b10 -`define AluBitwiseCtrlEnum_binary_sequancial_SRC1 'b11 +`define AluBitwiseCtrlEnum_binary_sequancial_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_binary_sequancial_OR_1 2'b01 +`define AluBitwiseCtrlEnum_binary_sequancial_AND_1 2'b10 +`define AluBitwiseCtrlEnum_binary_sequancial_SRC1 2'b11 -module VexRiscv -( - output rvfi_valid, - output [63:0] rvfi_order, - output [31:0] rvfi_insn, - output reg rvfi_trap, - output rvfi_halt, - output rvfi_intr, - output [4:0] rvfi_rs1_addr, - output [31:0] rvfi_rs1_rdata, - output [4:0] rvfi_rs2_addr, - output [31:0] rvfi_rs2_rdata, - output [4:0] rvfi_rd_addr, - output [31:0] rvfi_rd_wdata, - output [31:0] rvfi_pc_rdata, - output [31:0] rvfi_pc_wdata, - output [31:0] rvfi_mem_addr, - output [3:0] rvfi_mem_rmask, - output [3:0] rvfi_mem_wmask, - output [31:0] rvfi_mem_rdata, - output [31:0] rvfi_mem_wdata, - output iBus_cmd_valid, - input iBus_cmd_ready, - output [31:0] iBus_cmd_payload_pc, - input iBus_rsp_ready, - input iBus_rsp_error, - input [31:0] iBus_rsp_inst, - output dBus_cmd_valid, - input dBus_cmd_ready, - output dBus_cmd_payload_wr, - output [31:0] dBus_cmd_payload_address, - output [31:0] dBus_cmd_payload_data, - output [1:0] dBus_cmd_payload_size, - input dBus_rsp_ready, - input dBus_rsp_error, - input [31:0] dBus_rsp_data, - input clk, - input reset -); +`define ShiftCtrlEnum_binary_sequancial_type [1:0] +`define ShiftCtrlEnum_binary_sequancial_DISABLE_1 2'b00 +`define ShiftCtrlEnum_binary_sequancial_SLL_1 2'b01 +`define ShiftCtrlEnum_binary_sequancial_SRL_1 2'b10 +`define ShiftCtrlEnum_binary_sequancial_SRA_1 2'b11 + +`define Src1CtrlEnum_binary_sequancial_type [1:0] +`define Src1CtrlEnum_binary_sequancial_RS 2'b00 +`define Src1CtrlEnum_binary_sequancial_IMU 2'b01 +`define Src1CtrlEnum_binary_sequancial_FOUR 2'b10 +module VexRiscv ( + output rvfi_valid, + output [63:0] rvfi_order, + output [31:0] rvfi_insn, + output reg rvfi_trap, + output rvfi_halt, + output rvfi_intr, + output [4:0] rvfi_rs1_addr, + output [31:0] rvfi_rs1_rdata, + output [4:0] rvfi_rs2_addr, + output [31:0] rvfi_rs2_rdata, + output [4:0] rvfi_rd_addr, + output [31:0] rvfi_rd_wdata, + output [31:0] rvfi_pc_rdata, + output [31:0] rvfi_pc_wdata, + output [31:0] rvfi_mem_addr, + output [3:0] rvfi_mem_rmask, + output [3:0] rvfi_mem_wmask, + output [31:0] rvfi_mem_rdata, + output [31:0] rvfi_mem_wdata, + output iBus_cmd_valid, + input iBus_cmd_ready, + output [31:0] iBus_cmd_payload_pc, + input iBus_rsp_ready, + input iBus_rsp_error, + input [31:0] iBus_rsp_inst, + output dBus_cmd_valid, + input dBus_cmd_ready, + output dBus_cmd_payload_wr, + output [31:0] dBus_cmd_payload_address, + output [31:0] dBus_cmd_payload_data, + output [1:0] dBus_cmd_payload_size, + input dBus_rsp_ready, + input dBus_rsp_error, + input [31:0] dBus_rsp_data, + input clk, + input reset); + reg [31:0] zz_202; + reg [31:0] zz_203; + reg zz_204; + reg zz_205; + wire zz_206; + wire [1:0] zz_207; + wire [31:0] zz_208; + wire zz_209; + wire zz_210; + wire [31:0] zz_211; + wire [1:0] zz_212; + wire [31:0] zz_213; + wire [0:0] zz_214; + wire [0:0] zz_215; + wire [0:0] zz_216; + wire [0:0] zz_217; + wire [0:0] zz_218; + wire [0:0] zz_219; + wire [0:0] zz_220; + wire [0:0] zz_221; + wire [11:0] zz_222; + wire [11:0] zz_223; + wire [31:0] zz_224; + wire [31:0] zz_225; + wire [31:0] zz_226; + wire [31:0] zz_227; + wire [31:0] zz_228; + wire [1:0] zz_229; + wire [1:0] zz_230; + wire [1:0] zz_231; + wire [32:0] zz_232; + wire [31:0] zz_233; + wire [32:0] zz_234; + wire [19:0] zz_235; + wire [11:0] zz_236; + wire [11:0] zz_237; + wire [31:0] writeBack_FORMAL_MEM_ADDR; + wire [31:0] memory_FORMAL_MEM_ADDR; + wire [31:0] execute_FORMAL_MEM_ADDR; + wire execute_BRANCH_DO; + wire `BranchCtrlEnum_binary_sequancial_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequancial_type zz_1; + wire `BranchCtrlEnum_binary_sequancial_type zz_2; + wire `BranchCtrlEnum_binary_sequancial_type zz_3; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire `AluBitwiseCtrlEnum_binary_sequancial_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequancial_type zz_4; + wire `AluBitwiseCtrlEnum_binary_sequancial_type zz_5; + wire `AluBitwiseCtrlEnum_binary_sequancial_type zz_6; + wire [31:0] memory_PC; + wire [31:0] fetch_PC; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] execute_SHIFT_RIGHT; + wire `ShiftCtrlEnum_binary_sequancial_type zz_7; + wire `ShiftCtrlEnum_binary_sequancial_type zz_8; + wire `ShiftCtrlEnum_binary_sequancial_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequancial_type zz_9; + wire `ShiftCtrlEnum_binary_sequancial_type zz_10; + wire `ShiftCtrlEnum_binary_sequancial_type zz_11; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] fetch_FORMAL_PC_NEXT; + wire [31:0] prefetch_FORMAL_PC_NEXT; + wire [31:0] decode_SRC1; + wire [3:0] writeBack_FORMAL_MEM_RMASK; + wire [3:0] memory_FORMAL_MEM_RMASK; + wire [3:0] execute_FORMAL_MEM_RMASK; + wire writeBack_RS2_USE; + wire memory_RS2_USE; + wire execute_RS2_USE; + wire [31:0] writeBack_RS1; + wire [31:0] memory_RS1; + wire [31:0] decode_RS1; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire [31:0] memory_MEMORY_READ_DATA; + wire [31:0] writeBack_FORMAL_MEM_WDATA; + wire [31:0] memory_FORMAL_MEM_WDATA; + wire [31:0] execute_FORMAL_MEM_WDATA; + wire decode_MEMORY_ENABLE; + wire [31:0] fetch_INSTRUCTION; + wire writeBack_RS1_USE; + wire memory_RS1_USE; + wire execute_RS1_USE; + wire [31:0] writeBack_RS2; + wire [31:0] memory_RS2; + wire [31:0] decode_RS2; + wire [3:0] writeBack_FORMAL_MEM_WMASK; + wire [3:0] memory_FORMAL_MEM_WMASK; + wire [3:0] execute_FORMAL_MEM_WMASK; + wire decode_SRC_LESS_UNSIGNED; + wire writeBack_FORMAL_HALT; + wire memory_FORMAL_HALT; + wire execute_FORMAL_HALT; + wire decode_FORMAL_HALT; + wire fetch_FORMAL_HALT; + wire prefetch_FORMAL_HALT; + wire [31:0] writeBack_FORMAL_MEM_RDATA; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire `AluCtrlEnum_binary_sequancial_type decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequancial_type zz_12; + wire `AluCtrlEnum_binary_sequancial_type zz_13; + wire `AluCtrlEnum_binary_sequancial_type zz_14; + wire [31:0] execute_BRANCH_CALC; + wire [31:0] decode_SRC2; + wire decode_SRC_USE_SUB_LESS; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] zz_15; + wire [31:0] execute_PC; + wire [31:0] execute_RS1; + wire `BranchCtrlEnum_binary_sequancial_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequancial_type zz_16; + wire zz_17; + wire decode_RS2_USE; + wire decode_RS1_USE; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] zz_18; + wire `ShiftCtrlEnum_binary_sequancial_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequancial_type zz_19; + wire [31:0] zz_20; + wire `ShiftCtrlEnum_binary_sequancial_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequancial_type zz_21; + wire zz_22; + wire [31:0] zz_23; + wire [31:0] zz_24; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] zz_25; + wire [31:0] zz_26; + wire `Src2CtrlEnum_binary_sequancial_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequancial_type zz_27; + wire [31:0] zz_28; + wire [31:0] zz_29; + wire `Src1CtrlEnum_binary_sequancial_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequancial_type zz_30; + wire [31:0] zz_31; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_binary_sequancial_type execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequancial_type zz_32; + wire [31:0] zz_33; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_binary_sequancial_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequancial_type zz_34; + reg zz_35; + wire [31:0] zz_36; + wire [31:0] zz_37; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire decode_INSTRUCTION_READY; + wire `Src1CtrlEnum_binary_sequancial_type zz_38; + wire zz_39; + wire zz_40; + wire zz_41; + wire zz_42; + wire zz_43; + wire zz_44; + wire zz_45; + wire `ShiftCtrlEnum_binary_sequancial_type zz_46; + wire `AluCtrlEnum_binary_sequancial_type zz_47; + wire zz_48; + wire `BranchCtrlEnum_binary_sequancial_type zz_49; + wire `AluBitwiseCtrlEnum_binary_sequancial_type zz_50; + wire `Src2CtrlEnum_binary_sequancial_type zz_51; + wire zz_52; + wire [31:0] zz_53; + wire writeBack_MEMORY_ENABLE; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire [31:0] writeBack_MEMORY_READ_DATA; + wire [31:0] memory_INSTRUCTION; + wire memory_MEMORY_ENABLE; + wire [31:0] zz_54; + wire [31:0] zz_55; + wire [3:0] zz_56; + wire [3:0] zz_57; + wire [31:0] zz_58; + wire [1:0] zz_59; + wire [31:0] execute_RS2; + wire [31:0] execute_SRC_ADD; + wire [31:0] execute_INSTRUCTION; + wire execute_ALIGNEMENT_FAULT; + wire execute_MEMORY_ENABLE; + wire zz_60; + wire zz_61; + wire [31:0] zz_62; + wire [31:0] zz_63; + reg [31:0] zz_64; + wire [31:0] zz_65; + reg [31:0] zz_66; + wire [31:0] prefetch_PC; + wire [31:0] zz_67; + wire [31:0] zz_68; + wire [31:0] prefetch_PC_CALC_WITHOUT_JUMP; + wire [31:0] zz_69; + wire zz_70; + reg zz_71; + wire zz_72; + reg zz_73; + wire zz_74; + wire zz_75; + reg [31:0] zz_76; + wire zz_77; + wire zz_78; + wire zz_79; + wire [31:0] zz_80; + wire [31:0] writeBack_PC/* verilator public */ ; + wire [31:0] writeBack_INSTRUCTION/* verilator public */ ; + wire [31:0] decode_PC/* verilator public */ ; + wire [31:0] decode_INSTRUCTION/* verilator public */ ; reg prefetch_arbitration_haltItself; wire prefetch_arbitration_haltByOther; wire prefetch_arbitration_removeIt; - wire _1; + wire prefetch_arbitration_flushAll; reg prefetch_arbitration_isValid; wire prefetch_arbitration_isStuck; wire prefetch_arbitration_isStuckByOthers; + wire prefetch_arbitration_isFlushed; wire prefetch_arbitration_isFiring; reg fetch_arbitration_haltItself; wire fetch_arbitration_haltByOther; reg fetch_arbitration_removeIt; wire fetch_arbitration_flushAll; - wire _2; reg fetch_arbitration_isValid; wire fetch_arbitration_isStuck; wire fetch_arbitration_isStuckByOthers; wire fetch_arbitration_isFlushed; + wire fetch_arbitration_isFiring; reg decode_arbitration_haltItself/* verilator public */ ; wire decode_arbitration_haltByOther; reg decode_arbitration_removeIt; wire decode_arbitration_flushAll; - wire _3; reg decode_arbitration_isValid/* verilator public */ ; wire decode_arbitration_isStuck; wire decode_arbitration_isStuckByOthers; wire decode_arbitration_isFlushed; + wire decode_arbitration_isFiring; reg execute_arbitration_haltItself; wire execute_arbitration_haltByOther; reg execute_arbitration_removeIt; reg execute_arbitration_flushAll; - wire _4; reg execute_arbitration_isValid; wire execute_arbitration_isStuck; wire execute_arbitration_isStuckByOthers; wire execute_arbitration_isFlushed; + wire execute_arbitration_isFiring; reg memory_arbitration_haltItself; wire memory_arbitration_haltByOther; reg memory_arbitration_removeIt; wire memory_arbitration_flushAll; - wire _5; reg memory_arbitration_isValid; wire memory_arbitration_isStuck; wire memory_arbitration_isStuckByOthers; @@ -126,1070 +345,653 @@ module VexRiscv wire writeBack_arbitration_haltByOther; reg writeBack_arbitration_removeIt; wire writeBack_arbitration_flushAll; - wire _6; reg writeBack_arbitration_isValid/* verilator public */ ; wire writeBack_arbitration_isStuck; wire writeBack_arbitration_isStuckByOthers; wire writeBack_arbitration_isFlushed; wire writeBack_arbitration_isFiring/* verilator public */ ; - reg [31:0] decode_INSTRUCTION/* verilator public */ ; - wire [31:0] decode_PC/* verilator public */ ; - reg [31:0] writeBack_INSTRUCTION/* verilator public */ ; - wire [31:0] writeBack_PC/* verilator public */ ; wire decodeExceptionPort_valid; - wire _7; - wire [31:0] _8; - wire _9; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire zz_81; + wire [31:0] zz_82; reg [63:0] writeBack_FomalPlugin_order; - wire [63:0] _10; - wire [31:0] _11; - wire _12; - wire _13; - wire _14; - wire _15; - wire [4:0] _16; - wire [4:0] _17; - wire _18; - wire [4:0] _19; - wire [4:0] _20; - wire _21; - wire [4:0] _22; - wire [4:0] _23; - reg [31:0] _24; reg writeBack_FomalPlugin_haltRequest; - wire _25; - wire _26; - wire _27; - wire _28; - wire _29; - wire _30; - wire _31; - reg _32; - wire _33; - wire _34; - wire _35; - wire _36; - wire _37; - reg _38; - wire _39; - wire _40; - wire _41; - wire _42; - wire _43; - reg _44; - reg _45; - reg _46; - reg _47; - reg _48; - wire _49; - wire _50; - wire _51; - wire _52; + wire zz_83; + reg zz_84; + reg zz_85; + reg zz_86; + reg zz_87; + reg zz_88; reg writeBack_FomalPlugin_haltFired; - wire _53; - wire _54; - wire _55; - wire _56; - wire _57; - wire _58; - wire _59; - wire _60; - wire _61; - wire _62; reg [31:0] prefetch_PcManagerSimplePlugin_pcReg/* verilator public */ ; - wire _63; reg prefetch_PcManagerSimplePlugin_inc; - wire [1:0] _64; - wire [2:0] _65; wire [31:0] prefetch_PcManagerSimplePlugin_pcBeforeJumps; reg [31:0] prefetch_PcManagerSimplePlugin_pc; - wire [31:0] prefetch_PC_CALC_WITHOUT_JUMP; reg prefetch_PcManagerSimplePlugin_samplePcNext; wire prefetch_PcManagerSimplePlugin_jump_pcLoad_valid; wire [31:0] prefetch_PcManagerSimplePlugin_jump_pcLoad_payload; - wire _66; - wire _67; - wire _68; - wire _69; - wire _70; - wire [31:0] prefetch_PC; - wire [31:0] _71; - reg [31:0] _72; - wire _73; reg prefetch_IBusSimplePlugin_pendingCmd; - wire _74; - wire _75; - wire [31:0] _76; - wire _77; - wire _78; - wire _79; - reg _80; - wire _81; - wire _82; - reg [31:0] _83; - reg [31:0] _84; - wire _85; - wire _86; - wire [31:0] _87; - wire _88; - wire _89; - reg execute_MEMORY_ENABLE; - wire execute_ALIGNEMENT_FAULT; - reg [31:0] execute_INSTRUCTION; - wire [31:0] execute_SRC_ADD; - wire [31:0] _90; - wire [1:0] _91; - reg [31:0] execute_RS2; - reg [31:0] _92; - wire _93; - wire _94; - wire [1:0] _95; - wire [3:0] _96; - wire [3:0] _97; - wire [3:0] _98; + reg zz_89; + reg [31:0] zz_90; + reg [31:0] zz_91; reg [3:0] execute_DBusSimplePlugin_formalMask; - wire [3:0] _99; - wire [3:0] _100; - reg memory_MEMORY_ENABLE; - reg [31:0] memory_INSTRUCTION; - wire _101; - wire _102; reg [31:0] writeBack_DBusSimplePlugin_rspShifted; - reg [31:0] writeBack_MEMORY_READ_DATA; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; - wire [1:0] _103; - wire [1:0] _104; - wire [1:0] _105; - wire _106; - reg [31:0] _107; - wire _108; - reg [31:0] _109; + wire zz_92; + reg [31:0] zz_93; + wire zz_94; + reg [31:0] zz_95; reg [31:0] writeBack_DBusSimplePlugin_rspFormated; - reg writeBack_MEMORY_ENABLE; - wire _110; - wire [19:0] _111; - wire _112; - wire _113; - wire _114; - wire _115; - wire _116; - wire _117; - wire _118; - wire _119; - wire [31:0] _120; - wire [31:0] _121; - wire [31:0] _122; - wire [31:0] _123; - wire [31:0] _124; - wire [0:0] _125; - wire [0:0] _126; - wire [0:0] _127; - wire [0:0] _128; - wire [0:0] _129; - wire [0:0] _130; - wire [0:0] _131; - wire [0:0] _132; - wire decode_INSTRUCTION_READY; - wire decode_LEGAL_INSTRUCTION; - reg [31:0] RegFilePlugin_regFile [0:31]/* verilator public */ ; - reg decode_REGFILE_WRITE_VALID; - wire _133; - wire [31:0] decode_INSTRUCTION_ANTICIPATED; + wire [19:0] zz_96; + wire zz_97; + wire zz_98; + wire zz_99; + wire zz_100; + wire zz_101; + wire zz_102; + wire zz_103; + wire zz_104; + wire `Src2CtrlEnum_binary_sequancial_type zz_105; + wire `AluBitwiseCtrlEnum_binary_sequancial_type zz_106; + wire `BranchCtrlEnum_binary_sequancial_type zz_107; + wire `AluCtrlEnum_binary_sequancial_type zz_108; + wire `ShiftCtrlEnum_binary_sequancial_type zz_109; + wire `Src1CtrlEnum_binary_sequancial_type zz_110; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; - reg [31:0] RegFilePlugin_regFile_port0_data; - wire [4:0] RegFilePlugin_regFile_port0_address; - wire RegFilePlugin_regFile_port0_enable; - wire _134; + wire zz_111; wire [31:0] decode_RegFilePlugin_rs2Data; - reg [31:0] RegFilePlugin_regFile_port1_data; - wire [4:0] RegFilePlugin_regFile_port1_address; - wire RegFilePlugin_regFile_port1_enable; - wire _135; + wire zz_112; reg writeBack_RegFilePlugin_regFileWrite_valid/* verilator public */ ; wire [4:0] writeBack_RegFilePlugin_regFileWrite_payload_address/* verilator public */ ; wire [31:0] writeBack_RegFilePlugin_regFileWrite_payload_data/* verilator public */ ; - wire [4:0] RegFilePlugin_regFile_port2_address; - wire [31:0] RegFilePlugin_regFile_port2_data; - wire RegFilePlugin_regFile_port2_enable; - wire [4:0] _136; - wire _137; - reg _138; - wire _139; - wire _140; - reg `AluBitwiseCtrlEnum_binary_sequancial_type execute_ALU_BITWISE_CTRL; - reg [31:0] execute_SRC1; - reg [31:0] execute_SRC2; + reg zz_113; reg [31:0] execute_IntAluPlugin_bitwise; - wire `AluBitwiseCtrlEnum_binary_sequancial_type _141; - wire `AluBitwiseCtrlEnum_binary_sequancial_type _142; - wire `AluBitwiseCtrlEnum_binary_sequancial_type _143; - reg `AluCtrlEnum_binary_sequancial_type execute_ALU_CTRL; - wire execute_SRC_LESS; - wire [31:0] _144; - wire [31:0] execute_SRC_ADD_SUB; - reg [31:0] _145; - wire `AluCtrlEnum_binary_sequancial_type _146; - wire `AluCtrlEnum_binary_sequancial_type _147; - wire `Src1CtrlEnum_binary_sequancial_type decode_SRC1_CTRL; - wire [31:0] _148; - wire [11:0] _149; - reg [31:0] _150; - wire `Src1CtrlEnum_binary_sequancial_type _151; - wire `Src1CtrlEnum_binary_sequancial_type _152; - wire `Src2CtrlEnum_binary_sequancial_type decode_SRC2_CTRL; - wire [31:0] _153; - wire [11:0] _154; - wire _155; - reg [19:0] _156; - wire [11:0] _157; - wire _158; - reg [19:0] _159; - wire [31:0] _160; - reg [31:0] _161; - wire `Src2CtrlEnum_binary_sequancial_type _162; - wire `Src2CtrlEnum_binary_sequancial_type _163; - wire `Src2CtrlEnum_binary_sequancial_type _164; - wire [31:0] _165; - reg execute_SRC_USE_SUB_LESS; - wire [31:0] _166; - wire [31:0] _167; - wire [1:0] _168; - wire [1:0] _169; - wire [31:0] _170; + reg [31:0] zz_114; + reg [31:0] zz_115; + wire zz_116; + reg [19:0] zz_117; + wire zz_118; + reg [19:0] zz_119; + reg [31:0] zz_120; wire [31:0] execute_SrcPlugin_addSub; - reg execute_SRC_LESS_UNSIGNED; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrielShifterPlugin_amplitude; - reg `ShiftCtrlEnum_binary_sequancial_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_binary_sequancial_type _171; - reg [31:0] _172; + reg [31:0] zz_121; wire [31:0] execute_FullBarrielShifterPlugin_reversed; - wire `ShiftCtrlEnum_binary_sequancial_type _173; - wire [32:0] _174; - wire [32:0] _175; - wire [31:0] _176; - reg `ShiftCtrlEnum_binary_sequancial_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_binary_sequancial_type _177; - reg [31:0] _178; - reg [31:0] memory_SHIFT_RIGHT; - reg [31:0] _179; - wire `ShiftCtrlEnum_binary_sequancial_type _180; - wire `ShiftCtrlEnum_binary_sequancial_type _181; - reg _182; - reg _183; - reg _184; - reg [4:0] _185; - wire _186; - wire _187; - wire _188; - wire _189; - wire _190; - wire _191; - reg writeBack_REGFILE_WRITE_VALID; - wire _192; - wire _193; - wire _194; - wire _195; - wire _196; - reg memory_BYPASSABLE_MEMORY_STAGE; - reg memory_REGFILE_WRITE_VALID; - wire _197; - wire _198; - wire _199; - wire _200; - wire _201; - reg execute_BYPASSABLE_EXECUTE_STAGE; - reg execute_REGFILE_WRITE_VALID; - wire _202; - wire _203; - wire _204; - wire _205; - wire _206; - wire decode_RS1_USE; - wire _207; - wire decode_RS2_USE; - wire _208; - wire _209; + reg [31:0] zz_122; + reg zz_123; + reg zz_124; + reg zz_125; + reg [4:0] zz_126; wire execute_BranchPlugin_eq; - reg `BranchCtrlEnum_binary_sequancial_type execute_BRANCH_CTRL; - wire _210; - wire _211; - wire _212; - wire [2:0] _213; - wire [2:0] _214; - wire [2:0] _215; - reg _216; - wire [2:0] _217; - wire [2:0] _218; - reg _219; - wire `BranchCtrlEnum_binary_sequancial_type _220; - wire `BranchCtrlEnum_binary_sequancial_type _221; - wire `BranchCtrlEnum_binary_sequancial_type _222; - wire `BranchCtrlEnum_binary_sequancial_type _223; - reg [31:0] execute_RS1; - wire [31:0] _224; - wire [31:0] execute_PC; + wire [2:0] zz_127; + reg zz_128; + reg zz_129; wire [31:0] execute_BranchPlugin_branch_src1; - wire [19:0] _225; - wire _226; - reg [10:0] _227; - wire _228; - wire [11:0] _229; - wire _230; - reg [19:0] _231; - wire [11:0] _232; - wire _233; - reg [18:0] _234; - wire _235; - reg [31:0] _236; - wire `BranchCtrlEnum_binary_sequancial_type _237; - wire `BranchCtrlEnum_binary_sequancial_type _238; + wire zz_130; + reg [10:0] zz_131; + wire zz_132; + reg [19:0] zz_133; + wire zz_134; + reg [18:0] zz_135; + reg [31:0] zz_136; wire [31:0] execute_BranchPlugin_branch_src2; wire [31:0] execute_BranchPlugin_branchAdder; - wire [30:0] _239; - wire `BranchCtrlEnum_binary_sequancial_type _240; - wire _241; - wire [31:0] _242; - reg memory_BRANCH_DO; - wire [31:0] memory_BRANCH_CALC; - wire _243; - wire _244; - wire [1:0] _245; - wire [31:0] execute_REGFILE_WRITE_DATA; - reg [31:0] memory_REGFILE_WRITE_DATA; - reg [31:0] writeBack_REGFILE_WRITE_DATA; - reg execute_RS2_USE; - reg memory_RS2_USE; - reg writeBack_RS2_USE; - wire [31:0] decode_RS1; - reg [31:0] memory_RS1; - reg [31:0] writeBack_RS1; - wire [31:0] decode_RS2; - reg [31:0] memory_RS2; - reg [31:0] writeBack_RS2; - wire [31:0] execute_FORMAL_MEM_WDATA; - reg [31:0] memory_FORMAL_MEM_WDATA; - reg [31:0] writeBack_FORMAL_MEM_WDATA; - wire [31:0] execute_BRANCH_CALC; - reg [31:0] _246; - wire [31:0] fetch_PC; - wire [31:0] memory_PC; - reg [31:0] _247; - reg [31:0] _248; - reg [31:0] _249; - reg [31:0] _250; - reg [31:0] _251; - wire execute_BRANCH_DO; - wire [1:0] execute_MEMORY_ADDRESS_LOW; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - reg [1:0] _252; - reg [1:0] _253; - wire [31:0] decode_SRC2; - wire decode_BYPASSABLE_EXECUTE_STAGE; - reg execute_RS1_USE; - reg memory_RS1_USE; - reg writeBack_RS1_USE; - wire [3:0] execute_FORMAL_MEM_RMASK; - reg [3:0] memory_FORMAL_MEM_RMASK; - reg [3:0] writeBack_FORMAL_MEM_RMASK; - wire [31:0] execute_FORMAL_MEM_ADDR; - wire [31:0] memory_FORMAL_MEM_ADDR; - wire [31:0] writeBack_FORMAL_MEM_ADDR; - reg [31:0] _254; - reg [31:0] _255; - wire prefetch_FORMAL_HALT; - reg fetch_FORMAL_HALT; - reg decode_FORMAL_HALT; - reg execute_FORMAL_HALT; - reg memory_FORMAL_HALT; - reg writeBack_FORMAL_HALT; - wire `BranchCtrlEnum_binary_sequancial_type decode_BRANCH_CTRL; - wire decode_SRC_LESS_UNSIGNED; - wire `AluBitwiseCtrlEnum_binary_sequancial_type decode_ALU_BITWISE_CTRL; - wire [3:0] execute_FORMAL_MEM_WMASK; - reg [3:0] memory_FORMAL_MEM_WMASK; - reg [3:0] writeBack_FORMAL_MEM_WMASK; - wire [31:0] writeBack_FORMAL_MEM_RDATA; - wire [31:0] fetch_INSTRUCTION; - wire [31:0] prefetch_FORMAL_PC_NEXT; - wire [31:0] fetch_FORMAL_PC_NEXT; - wire [31:0] decode_FORMAL_PC_NEXT; - wire [31:0] execute_FORMAL_PC_NEXT; - wire [31:0] memory_FORMAL_PC_NEXT; - wire [31:0] writeBack_FORMAL_PC_NEXT; - reg [31:0] _256; - reg [31:0] _257; - reg [31:0] _258; - reg [31:0] _259; - reg [31:0] _260; - wire `AluCtrlEnum_binary_sequancial_type decode_ALU_CTRL; - wire [31:0] memory_MEMORY_READ_DATA; - wire [31:0] execute_SHIFT_RIGHT; - wire decode_BYPASSABLE_MEMORY_STAGE; - reg execute_BYPASSABLE_MEMORY_STAGE; - wire decode_MEMORY_ENABLE; - wire [31:0] decode_SRC1; - wire `ShiftCtrlEnum_binary_sequancial_type decode_SHIFT_CTRL; - wire decode_SRC_USE_SUB_LESS; - wire _261; - wire _262; - wire _263; - wire _264; - wire _265; - wire _266; - wire _267; - wire _268; - wire _269; - wire _270; - wire _271; - wire _272; - wire _273; - wire _274; - wire _275; - wire _276; - wire _277; - wire _278; - wire _279; - wire _280; - wire _281; - wire _282; - wire _283; - wire _284; - wire [31:0] _285; - reg _286; - reg _287; - wire [1:0] _288; - wire _289; - wire _290; - wire [31:0] _291; - wire [31:0] _292; - wire [1:0] _293; - wire [31:0] _294; - wire [4:0] _295; - wire [4:0] _296; - wire [4:0] _297; - assign prefetch_arbitration_haltByOther = 1'b0; - assign prefetch_arbitration_removeIt = 1'b0; - assign _1 = 1'b0; - assign prefetch_arbitration_isStuck = (prefetch_arbitration_haltItself || prefetch_arbitration_isStuckByOthers); - assign prefetch_arbitration_isStuckByOthers = (prefetch_arbitration_haltByOther || (((((_273 || fetch_arbitration_haltItself) || decode_arbitration_haltItself) || execute_arbitration_haltItself) || memory_arbitration_haltItself) || writeBack_arbitration_haltItself)); - assign prefetch_arbitration_isFiring = ((prefetch_arbitration_isValid && (! prefetch_arbitration_isStuck)) && (! prefetch_arbitration_removeIt)); - assign fetch_arbitration_haltByOther = 1'b0; - assign fetch_arbitration_flushAll = 1'b0; - assign _2 = 1'b0; - assign fetch_arbitration_isStuck = (fetch_arbitration_haltItself || fetch_arbitration_isStuckByOthers); - assign fetch_arbitration_isStuckByOthers = (fetch_arbitration_haltByOther || ((((_274 || decode_arbitration_haltItself) || execute_arbitration_haltItself) || memory_arbitration_haltItself) || writeBack_arbitration_haltItself)); - assign fetch_arbitration_isFlushed = ((((fetch_arbitration_flushAll || decode_arbitration_flushAll) || execute_arbitration_flushAll) || memory_arbitration_flushAll) || writeBack_arbitration_flushAll); - assign decode_arbitration_haltByOther = 1'b0; - assign decode_arbitration_flushAll = 1'b0; - assign _3 = 1'b0; - assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); - assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((_275 || execute_arbitration_haltItself) || memory_arbitration_haltItself) || writeBack_arbitration_haltItself)); - assign decode_arbitration_isFlushed = (((decode_arbitration_flushAll || execute_arbitration_flushAll) || memory_arbitration_flushAll) || writeBack_arbitration_flushAll); - assign execute_arbitration_haltByOther = 1'b0; - assign _4 = 1'b0; - assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); - assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((_276 || memory_arbitration_haltItself) || writeBack_arbitration_haltItself)); - assign execute_arbitration_isFlushed = ((execute_arbitration_flushAll || memory_arbitration_flushAll) || writeBack_arbitration_flushAll); - assign memory_arbitration_haltByOther = 1'b0; - assign memory_arbitration_flushAll = 1'b0; - assign _5 = 1'b0; - assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); - assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (_277 || writeBack_arbitration_haltItself)); - assign memory_arbitration_isFlushed = (memory_arbitration_flushAll || writeBack_arbitration_flushAll); - assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); - assign writeBack_arbitration_haltItself = 1'b0; - assign writeBack_arbitration_haltByOther = 1'b0; - assign writeBack_arbitration_flushAll = 1'b0; - assign _6 = 1'b0; - assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); - assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || _278); - assign writeBack_arbitration_isFlushed = writeBack_arbitration_flushAll; - assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - assign decode_PC = _248; - assign writeBack_PC = _251; - assign rvfi_valid = _286; - assign rvfi_order = writeBack_FomalPlugin_order; - assign rvfi_insn = _11; - assign rvfi_halt = _287; - assign rvfi_intr = _14; - assign rvfi_rs1_addr = _17; - assign rvfi_rs1_rdata = (_15 ? writeBack_RS1 : (32'b00000000000000000000000000000000)); - assign rvfi_rs2_addr = _20; - assign rvfi_rs2_rdata = (_18 ? writeBack_RS2 : (32'b00000000000000000000000000000000)); - assign rvfi_rd_addr = _23; - assign rvfi_rd_wdata = (_21 ? _24 : (32'b00000000000000000000000000000000)); - assign rvfi_pc_rdata = writeBack_PC; - assign rvfi_pc_wdata = writeBack_FORMAL_PC_NEXT; - assign rvfi_mem_addr = writeBack_FORMAL_MEM_ADDR; - assign rvfi_mem_rmask = writeBack_FORMAL_MEM_RMASK; - assign rvfi_mem_wmask = writeBack_FORMAL_MEM_WMASK; - assign rvfi_mem_rdata = writeBack_FORMAL_MEM_RDATA; - assign rvfi_mem_wdata = writeBack_FORMAL_MEM_WDATA; - assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); - assign _7 = (memory_arbitration_isFiring && memory_BRANCH_DO); - assign _8 = memory_BRANCH_CALC; - assign _9 = ((memory_arbitration_isValid && memory_BRANCH_DO) && (_245 != (2'b00))); - assign _10 = (writeBack_FomalPlugin_order + (64'b0000000000000000000000000000000000000000000000000000000000000001)); - assign _11 = writeBack_INSTRUCTION; - assign _12 = 1'b0; - assign _13 = 1'b0; - assign _14 = 1'b0; - assign _15 = writeBack_RS1_USE; - assign _16 = _11[19 : 15]; - assign _17 = (_15 ? _16 : _295); - assign _18 = writeBack_RS2_USE; - assign _19 = _11[24 : 20]; - assign _20 = (_18 ? _19 : _296); - assign _21 = writeBack_REGFILE_WRITE_VALID; - assign _22 = _11[11 : 7]; - assign _23 = (_21 ? _22 : _297); - assign _25 = prefetch_FORMAL_HALT; - assign _26 = 1'b1; - assign _27 = 1'b1; - assign _28 = 1'b0; - assign _29 = fetch_FORMAL_HALT; - assign _30 = 1'b1; - assign _31 = 1'b1; - assign _33 = 1'b1; - assign _34 = 1'b1; - assign _35 = execute_FORMAL_HALT; - assign _36 = 1'b1; - assign _37 = 1'b1; - assign _39 = 1'b1; - assign _40 = 1'b1; - assign _41 = 1'b1; - assign _42 = 1'b1; - assign _43 = 1'b0; - assign _49 = 1'b1; - assign _50 = 1'b1; - assign _51 = 1'b1; - assign _52 = 1'b0; - assign _53 = 1'b1; - assign _54 = 1'b0; - assign _55 = 1'b0; - assign _56 = 1'b1; - assign _57 = 1'b1; - assign _58 = 1'b0; - assign _59 = 1'b1; - assign _60 = 1'b1; - assign _61 = 1'b0; - assign _62 = 1'b1; - assign _63 = 1'b0; - assign _64 = (2'b00); - assign _65 = {prefetch_PcManagerSimplePlugin_inc,_64}; - assign prefetch_PcManagerSimplePlugin_pcBeforeJumps = (prefetch_PcManagerSimplePlugin_pcReg + _294); - assign prefetch_PC_CALC_WITHOUT_JUMP = prefetch_PcManagerSimplePlugin_pcBeforeJumps; - assign prefetch_PcManagerSimplePlugin_jump_pcLoad_valid = _7; - assign prefetch_PcManagerSimplePlugin_jump_pcLoad_payload = _8; - assign _66 = 1'b0; - assign _67 = 1'b1; - assign _68 = 1'b0; - assign _69 = 1'b1; - assign _70 = 1'b1; - assign prefetch_PC = prefetch_PcManagerSimplePlugin_pc; - assign _71 = (prefetch_PC + (32'b00000000000000000000000000000100)); - assign iBus_cmd_valid = _284; - assign iBus_cmd_payload_pc = _76; - assign _73 = 1'b0; - assign _74 = 1'b0; - assign _75 = 1'b1; - assign _76 = prefetch_PC; - assign _77 = 1'b1; - assign _78 = 1'b0; - assign _79 = 1'b0; - assign _81 = 1'b1; - assign _82 = 1'b0; - assign _85 = 1'b1; - assign _86 = 1'b0; - assign _87 = fetch_INSTRUCTION; - assign _88 = 1'b1; - assign dBus_cmd_valid = _289; - assign dBus_cmd_payload_wr = _290; - assign dBus_cmd_payload_address = _285; - assign dBus_cmd_payload_data = _291; - assign dBus_cmd_payload_size = _288; - assign _89 = 1'b0; - assign execute_ALIGNEMENT_FAULT = _89; - assign execute_SRC_ADD = execute_SrcPlugin_addSub; - assign _90 = execute_SRC_ADD; - assign _91 = execute_INSTRUCTION[13 : 12]; - assign _93 = 1'b1; - assign _94 = 1'b0; - assign _95 = _285[1 : 0]; - assign _96 = (4'b0001); - assign _97 = (4'b0011); - assign _98 = (4'b1111); - assign _99 = (4'b0000); - assign _100 = (4'b0000); - assign _101 = 1'b1; - assign _102 = 1'b1; - assign writeBack_MEMORY_ADDRESS_LOW = _253; - assign _103 = (2'b10); - assign _104 = (2'b11); - assign _105 = writeBack_INSTRUCTION[13 : 12]; - assign _106 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - assign _108 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - assign _110 = 1'b1; - assign _111 = {({((decode_INSTRUCTION & (32'b00000000000000000001000000000000)) == (32'b00000000000000000001000000000000)),_115} != (2'b00)),{({_115,((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000010000000000000))} != (2'b00)),{({_117,{_115,_112}} != (3'b000)),{({_117,{_115,_118}} != (3'b000)),{({_117,_116} != (2'b00)),{(((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001000000)) != (1'b0)),{({_119,((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000100000))} != (2'b00)),{({_117,{_119,{_115,{_118,((decode_INSTRUCTION & (32'b00000000000000000100000001000000)) == (32'b00000000000000000100000000000000))}}}} != (5'b00000)),{({_117,_116} != (2'b00)),{(((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000100)) != (1'b0)),{({((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000000000)),((decode_INSTRUCTION & (32'b00000000000000000101000000000000)) == (32'b00000000000000000001000000000000))} != (2'b00)),{({((decode_INSTRUCTION & (32'b00000000000000000111000000010100)) == (32'b00000000000000000101000000010000)),((decode_INSTRUCTION & (32'b00000000000000000111000001100100)) == (32'b00000000000000000101000000100000))} != (2'b00)),{({((decode_INSTRUCTION & (32'b01000000000000000011000000010100)) == (32'b01000000000000000001000000010000)),{((decode_INSTRUCTION & (32'b01000000000000000100000001100100)) == (32'b01000000000000000100000000100000)),((decode_INSTRUCTION & (32'b00000000000000000111000000010100)) == (32'b00000000000000000001000000010000))}} != (3'b000)),{({_113,{((decode_INSTRUCTION & (32'b01000000000000000000000000110000)) == (32'b01000000000000000000000000110000)),((decode_INSTRUCTION & (32'b00000000000000000010000000010100)) == (32'b00000000000000000010000000010000))}} != (3'b000)),{({((decode_INSTRUCTION & (32'b00000000000000000100000000000100)) == (32'b00000000000000000100000000000000)),((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100100))} != (2'b00)),{(((decode_INSTRUCTION & (32'b00000000000000000110000000000100)) == (32'b00000000000000000010000000000000)) != (1'b0)),{({((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000000)),{_114,((decode_INSTRUCTION & (32'b00000000000000000000000000011000)) == (32'b00000000000000000000000000000000))}} != (3'b000)),{({_115,{((decode_INSTRUCTION & (32'b00000000000000000010000000100000)) == (32'b00000000000000000010000000100000)),{((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000010000)),{((decode_INSTRUCTION & (32'b00000000000000000001000000100000)) == (32'b00000000000000000000000000100000)),((decode_INSTRUCTION & (32'b00000000000000000001000000010000)) == (32'b00000000000000000000000000010000))}}}} != (5'b00000)),{(_114 != (1'b0)),({_113,{((decode_INSTRUCTION & (32'b00000000000000000000000000100100)) == (32'b00000000000000000000000000100000)),_112}} != (3'b000))}}}}}}}}}}}}}}}}}}}; - assign _112 = ((decode_INSTRUCTION & (32'b00000000000000000000000001110000)) == (32'b00000000000000000000000000100000)); - assign _113 = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000001000000)); - assign _114 = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000000000)); - assign _115 = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); - assign _116 = ((decode_INSTRUCTION & (32'b00000000000000000000000000010100)) == (32'b00000000000000000000000000000100)); - assign _117 = ((decode_INSTRUCTION & (32'b00000000000000000000000000001000)) == (32'b00000000000000000000000000001000)); - assign _118 = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000000000)); - assign _119 = ((decode_INSTRUCTION & (32'b00000000000000000000000000010000)) == (32'b00000000000000000000000000010000)); - assign _120 = (32'b10111110000000000111000001111111); - assign _121 = (32'b10111110000000000111000001111111); - assign _122 = (32'b11111100000000000011000001111111); - assign _123 = (32'b10111100000000000111000001111111); - assign _124 = (32'b11111110000000000000000001111111); - assign _125 = _111[0 : 0]; - assign _126 = _111[1 : 1]; - assign _127 = _111[2 : 2]; - assign _128 = _111[3 : 3]; - assign _129 = _111[6 : 6]; - assign _130 = _111[9 : 9]; - assign _131 = _111[12 : 12]; - assign _132 = _111[13 : 13]; - assign decode_INSTRUCTION_READY = _88; - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000001100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)),{((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & (32'b00000000000000000110000001011111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & (32'b00000000000000000101000001011111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & (32'b00000000000000000111000001111011)) == (32'b00000000000000000000000001100011)),{((decode_INSTRUCTION & _124) == (32'b00000000000000000000000000110011)),{((decode_INSTRUCTION & _123) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & _122) == (32'b00000000000000000001000000010011)),{((decode_INSTRUCTION & _121) == (32'b00000000000000000101000000110011)),((decode_INSTRUCTION & _120) == (32'b00000000000000000000000000110011))}}}}}}}}}}}}}}} != (16'b0000000000000000)); - assign _133 = 1'b0; - assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : _87); - assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; - assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = RegFilePlugin_regFile_port0_data; - assign RegFilePlugin_regFile_port0_address = decode_RegFilePlugin_regFileReadAddress1; - assign RegFilePlugin_regFile_port0_enable = _134; - assign _134 = 1'b1; - assign decode_RegFilePlugin_rs2Data = RegFilePlugin_regFile_port1_data; - assign RegFilePlugin_regFile_port1_address = decode_RegFilePlugin_regFileReadAddress2; - assign RegFilePlugin_regFile_port1_enable = _135; - assign _135 = 1'b1; - assign writeBack_RegFilePlugin_regFileWrite_payload_address = _136; - assign writeBack_RegFilePlugin_regFileWrite_payload_data = _24; - assign RegFilePlugin_regFile_port2_address = writeBack_RegFilePlugin_regFileWrite_payload_address; - assign RegFilePlugin_regFile_port2_data = writeBack_RegFilePlugin_regFileWrite_payload_data; - assign RegFilePlugin_regFile_port2_enable = writeBack_RegFilePlugin_regFileWrite_valid; - assign _136 = _11[11 : 7]; - assign _137 = 1'b0; - assign _139 = 1'b1; - assign _140 = 1'b1; - assign _141 = `AluBitwiseCtrlEnum_binary_sequancial_AND_1; - assign _142 = `AluBitwiseCtrlEnum_binary_sequancial_OR_1; - assign _143 = `AluBitwiseCtrlEnum_binary_sequancial_XOR_1; - assign execute_SRC_LESS = execute_SrcPlugin_less; - assign _144 = execute_SRC_LESS; - assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; - assign _146 = `AluCtrlEnum_binary_sequancial_BITWISE; - assign _147 = `AluCtrlEnum_binary_sequancial_SLT_SLTU; - assign decode_SRC1_CTRL = _111[11 : 10]; - assign _148 = decode_RS1; - assign _149 = (12'b000000000000); - assign _151 = `Src1CtrlEnum_binary_sequancial_RS; - assign _152 = `Src1CtrlEnum_binary_sequancial_FOUR; - assign decode_SRC2_CTRL = _111[17 : 16]; - assign _153 = decode_RS2; - assign _154 = decode_INSTRUCTION[31 : 20]; - assign _155 = _154[11]; - assign _157 = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}; - assign _158 = _157[11]; - assign _160 = decode_PC; - assign _162 = `Src2CtrlEnum_binary_sequancial_RS; - assign _163 = `Src2CtrlEnum_binary_sequancial_IMI; - assign _164 = `Src2CtrlEnum_binary_sequancial_IMS; - assign _165 = execute_SRC1; - assign _166 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _167 = ($signed(_165) + $signed(_166)); - assign _168 = (2'b01); - assign _169 = (execute_SRC_USE_SUB_LESS ? _168 : _293); - assign _170 = ($signed(_167) + $signed(_292)); - assign execute_SrcPlugin_addSub = _170; - assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); - assign execute_FullBarrielShifterPlugin_amplitude = execute_SRC2[4 : 0]; - assign _171 = `ShiftCtrlEnum_binary_sequancial_SLL_1; - assign execute_FullBarrielShifterPlugin_reversed = ((execute_SHIFT_CTRL == _171) ? _172 : execute_SRC1); - assign _173 = `ShiftCtrlEnum_binary_sequancial_SRA_1; - assign _174 = {((execute_SHIFT_CTRL == _173) && execute_FullBarrielShifterPlugin_reversed[31]),execute_FullBarrielShifterPlugin_reversed}; - assign _175 = ($signed(_174) >>> execute_FullBarrielShifterPlugin_amplitude); - assign _176 = _175[31 : 0]; - assign _177 = `ShiftCtrlEnum_binary_sequancial_SLL_1; - assign _180 = `ShiftCtrlEnum_binary_sequancial_SRL_1; - assign _181 = `ShiftCtrlEnum_binary_sequancial_SRA_1; - assign _186 = 1'b0; - assign _187 = 1'b1; - assign _188 = 1'b0; - assign _189 = 1'b1; - assign _190 = 1'b0; - assign _191 = 1'b1; - assign _192 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _193 = 1'b1; - assign _194 = (_193 || (! _191)); - assign _195 = 1'b1; - assign _196 = 1'b1; - assign _197 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _198 = 1'b1; - assign _199 = (_198 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _200 = 1'b1; - assign _201 = 1'b1; - assign _202 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _203 = 1'b1; - assign _204 = (_203 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _205 = 1'b1; - assign _206 = 1'b1; - assign decode_RS1_USE = _128[0]; - assign _207 = 1'b0; - assign decode_RS2_USE = _125[0]; - assign _208 = 1'b0; - assign _209 = 1'b1; - assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _210 = 1'b0; - assign _211 = 1'b1; - assign _212 = 1'b1; - assign _213 = execute_INSTRUCTION[14 : 12]; - assign _214 = (3'b000); - assign _215 = (3'b001); - assign _217 = (3'b101); - assign _218 = (3'b101); - assign _220 = `BranchCtrlEnum_binary_sequancial_INC; - assign _221 = `BranchCtrlEnum_binary_sequancial_JAL; - assign _222 = `BranchCtrlEnum_binary_sequancial_JALR; - assign _223 = `BranchCtrlEnum_binary_sequancial_JALR; - assign _224 = execute_RS1; - assign execute_PC = _249; - assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == _223) ? _224 : execute_PC); - assign _225 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _226 = _225[19]; - assign _228 = 1'b0; - assign _229 = execute_INSTRUCTION[31 : 20]; - assign _230 = _229[11]; - assign _232 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _233 = _232[11]; - assign _235 = 1'b0; - assign _237 = `BranchCtrlEnum_binary_sequancial_JAL; - assign _238 = `BranchCtrlEnum_binary_sequancial_JALR; - assign execute_BranchPlugin_branch_src2 = _236; - assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); - assign _239 = execute_BranchPlugin_branchAdder[31 : 1]; - assign _240 = `BranchCtrlEnum_binary_sequancial_JALR; - assign _241 = 1'b0; - assign _242 = {_239,((execute_BRANCH_CTRL == _240) ? _241 : execute_BranchPlugin_branchAdder[0])}; - assign memory_BRANCH_CALC = _246; - assign _243 = 1'b1; - assign _244 = 1'b0; - assign _245 = _8[1 : 0]; - assign execute_REGFILE_WRITE_DATA = _145; - assign decode_RS1 = decode_RegFilePlugin_rs1Data; - assign decode_RS2 = decode_RegFilePlugin_rs2Data; - assign execute_FORMAL_MEM_WDATA = _291; - assign execute_BRANCH_CALC = _242; - assign fetch_PC = _247; - assign memory_PC = _250; - assign execute_BRANCH_DO = _219; - assign execute_MEMORY_ADDRESS_LOW = _95; - assign memory_MEMORY_ADDRESS_LOW = _252; - assign decode_SRC2 = _161; - assign decode_BYPASSABLE_EXECUTE_STAGE = _127[0]; - assign execute_FORMAL_MEM_RMASK = ((_289 && (! _290)) ? execute_DBusSimplePlugin_formalMask : _100); - assign execute_FORMAL_MEM_ADDR = _285; - assign memory_FORMAL_MEM_ADDR = _254; - assign writeBack_FORMAL_MEM_ADDR = _255; - assign prefetch_FORMAL_HALT = _55; - assign decode_BRANCH_CTRL = _111[15 : 14]; - assign decode_SRC_LESS_UNSIGNED = _130[0]; - assign decode_ALU_BITWISE_CTRL = _111[19 : 18]; - assign execute_FORMAL_MEM_WMASK = ((_289 && _290) ? execute_DBusSimplePlugin_formalMask : _99); - assign writeBack_FORMAL_MEM_RDATA = writeBack_DBusSimplePlugin_rspFormated; - assign fetch_INSTRUCTION = _84; - assign prefetch_FORMAL_PC_NEXT = _71; - assign fetch_FORMAL_PC_NEXT = _256; - assign decode_FORMAL_PC_NEXT = _257; - assign execute_FORMAL_PC_NEXT = _258; - assign memory_FORMAL_PC_NEXT = _259; - assign writeBack_FORMAL_PC_NEXT = _260; - assign decode_ALU_CTRL = _111[5 : 4]; - assign memory_MEMORY_READ_DATA = dBus_rsp_data; - assign execute_SHIFT_RIGHT = _176; - assign decode_BYPASSABLE_MEMORY_STAGE = _132[0]; - assign decode_MEMORY_ENABLE = _126[0]; - assign decode_SRC1 = _150; - assign decode_SHIFT_CTRL = _111[8 : 7]; - assign decode_SRC_USE_SUB_LESS = _129[0]; - assign _261 = 1'b0; - assign _262 = 1'b1; - assign _263 = 1'b1; - assign _264 = 1'b0; - assign _265 = 1'b1; - assign _266 = 1'b0; - assign _267 = 1'b1; - assign _268 = 1'b0; - assign _269 = 1'b1; - assign _270 = 1'b0; - assign _271 = 1'b1; - assign _272 = 1'b0; - assign _273 = 1'b0; - assign _274 = 1'b0; - assign _275 = 1'b0; - assign _276 = 1'b0; - assign _277 = 1'b0; - assign _278 = 1'b0; - assign _279 = 1'b0; - assign _280 = 1'b0; - assign _281 = 1'b0; - assign _282 = 1'b0; - assign _283 = 1'b0; - assign _284 = (((prefetch_arbitration_isValid && (! prefetch_arbitration_removeIt)) && (! prefetch_arbitration_isStuckByOthers)) && (! (prefetch_IBusSimplePlugin_pendingCmd && (! iBus_rsp_ready)))); - assign _285 = _90; - assign _288 = _91; - assign _289 = ((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_removeIt)) && (! execute_ALIGNEMENT_FAULT)); - assign _290 = execute_INSTRUCTION[5]; - assign _291 = _92; - assign _292 = $signed(_169); - assign _293 = (2'b00); - assign _294 = _65; - assign _295 = (5'b00000); - assign _296 = (5'b00000); - assign _297 = (5'b00000); - always @ (iBus_cmd_ready or iBus_rsp_ready or prefetch_IBusSimplePlugin_pendingCmd or _77 or _78) + reg zz_137; + reg [31:0] zz_138; + reg [31:0] zz_139; + reg `AluCtrlEnum_binary_sequancial_type zz_140; + reg zz_141; + reg zz_142; + reg zz_143; + reg zz_144; + reg zz_145; + reg zz_146; + reg zz_147; + reg zz_148; + reg zz_149; + reg zz_150; + reg zz_151; + reg [3:0] zz_152; + reg [3:0] zz_153; + reg [31:0] zz_154; + reg [31:0] zz_155; + reg [31:0] zz_156; + reg zz_157; + reg zz_158; + reg zz_159; + reg [31:0] zz_160; + reg [31:0] zz_161; + reg [31:0] zz_162; + reg [31:0] zz_163; + reg zz_164; + reg zz_165; + reg zz_166; + reg [31:0] zz_167; + reg [31:0] zz_168; + reg [31:0] zz_169; + reg zz_170; + reg [31:0] zz_171; + reg [31:0] zz_172; + reg [31:0] zz_173; + reg zz_174; + reg zz_175; + reg zz_176; + reg [3:0] zz_177; + reg [3:0] zz_178; + reg [31:0] zz_179; + reg [31:0] zz_180; + reg [31:0] zz_181; + reg [31:0] zz_182; + reg [31:0] zz_183; + reg [31:0] zz_184; + reg `ShiftCtrlEnum_binary_sequancial_type zz_185; + reg `ShiftCtrlEnum_binary_sequancial_type zz_186; + reg [31:0] zz_187; + reg [1:0] zz_188; + reg [1:0] zz_189; + reg [31:0] zz_190; + reg [31:0] zz_191; + reg [31:0] zz_192; + reg [31:0] zz_193; + reg [31:0] zz_194; + reg `AluBitwiseCtrlEnum_binary_sequancial_type zz_195; + reg [31:0] zz_196; + reg [31:0] zz_197; + reg `BranchCtrlEnum_binary_sequancial_type zz_198; + reg zz_199; + reg [31:0] zz_200; + reg [31:0] zz_201; + reg [31:0] RegFilePlugin_regFile [0:31]/* verilator public */ ; + assign rvfi_valid = zz_204; + assign rvfi_halt = zz_205; + assign iBus_cmd_valid = zz_206; + assign dBus_cmd_payload_size = zz_207; + assign dBus_cmd_payload_address = zz_208; + assign dBus_cmd_valid = zz_209; + assign dBus_cmd_payload_wr = zz_210; + assign dBus_cmd_payload_data = zz_211; + assign zz_212 = writeBack_INSTRUCTION[13 : 12]; + assign zz_213 = {29'd0, {prefetch_PcManagerSimplePlugin_inc,(2'b00)}}; + assign zz_214 = zz_96[6 : 6]; + assign zz_215 = zz_96[11 : 11]; + assign zz_216 = zz_96[12 : 12]; + assign zz_217 = zz_96[13 : 13]; + assign zz_218 = zz_96[14 : 14]; + assign zz_219 = zz_96[15 : 15]; + assign zz_220 = zz_96[16 : 16]; + assign zz_221 = zz_96[17 : 17]; + assign zz_222 = decode_INSTRUCTION[31 : 20]; + assign zz_223 = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}; + assign zz_224 = ($signed(zz_225) + $signed(zz_228)); + assign zz_225 = ($signed(zz_226) + $signed(zz_227)); + assign zz_226 = execute_SRC1; + assign zz_227 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign zz_228 = {{30{zz_229[1]}}, zz_229}; + assign zz_229 = (execute_SRC_USE_SUB_LESS ? zz_230 : zz_231); + assign zz_230 = (2'b01); + assign zz_231 = (2'b00); + assign zz_232 = ($signed(zz_234) >>> execute_FullBarrielShifterPlugin_amplitude); + assign zz_233 = zz_232[31 : 0]; + assign zz_234 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequancial_SRA_1) && execute_FullBarrielShifterPlugin_reversed[31]),execute_FullBarrielShifterPlugin_reversed}; + assign zz_235 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign zz_236 = execute_INSTRUCTION[31 : 20]; + assign zz_237 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + always @ (posedge clk) begin - prefetch_arbitration_haltItself = _78; - if(((! iBus_cmd_ready) || (prefetch_IBusSimplePlugin_pendingCmd && (! iBus_rsp_ready))))begin - prefetch_arbitration_haltItself = _77; + if(zz_35) begin + RegFilePlugin_regFile[writeBack_RegFilePlugin_regFileWrite_payload_address] <= writeBack_RegFilePlugin_regFileWrite_payload_data; end end - always @ (fetch_arbitration_isValid or iBus_rsp_ready or _80 or _85 or _86) + always @ (posedge clk) begin - fetch_arbitration_haltItself = _86; - if(((fetch_arbitration_isValid && (! iBus_rsp_ready)) && (! _80)))begin - fetch_arbitration_haltItself = _85; + if(zz_111) begin + zz_202 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end - always @ (fetch_arbitration_isFlushed or _263 or _264) + always @ (posedge clk) begin - fetch_arbitration_removeIt = _264; - if(fetch_arbitration_isFlushed)begin - fetch_arbitration_removeIt = _263; + if(zz_112) begin + zz_203 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end - always @ (decode_arbitration_isValid or decodeExceptionPort_valid or _57 or _58 or _182 or _183 or _209) + assign writeBack_FORMAL_MEM_ADDR = zz_201; + assign memory_FORMAL_MEM_ADDR = zz_200; + assign execute_FORMAL_MEM_ADDR = zz_58; + assign execute_BRANCH_DO = zz_17; + assign decode_BRANCH_CTRL = zz_1; + assign zz_2 = zz_3; + assign writeBack_REGFILE_WRITE_DATA = zz_197; + assign memory_REGFILE_WRITE_DATA = zz_196; + assign execute_REGFILE_WRITE_DATA = zz_33; + assign decode_ALU_BITWISE_CTRL = zz_4; + assign zz_5 = zz_6; + assign memory_PC = zz_193; + assign fetch_PC = zz_190; + assign memory_MEMORY_ADDRESS_LOW = zz_188; + assign execute_MEMORY_ADDRESS_LOW = zz_59; + assign execute_SHIFT_RIGHT = zz_20; + assign zz_7 = zz_8; + assign decode_SHIFT_CTRL = zz_9; + assign zz_10 = zz_11; + assign writeBack_FORMAL_PC_NEXT = zz_184; + assign memory_FORMAL_PC_NEXT = zz_183; + assign execute_FORMAL_PC_NEXT = zz_182; + assign decode_FORMAL_PC_NEXT = zz_181; + assign fetch_FORMAL_PC_NEXT = zz_180; + assign prefetch_FORMAL_PC_NEXT = zz_67; + assign decode_SRC1 = zz_31; + assign writeBack_FORMAL_MEM_RMASK = zz_178; + assign memory_FORMAL_MEM_RMASK = zz_177; + assign execute_FORMAL_MEM_RMASK = zz_56; + assign writeBack_RS2_USE = zz_176; + assign memory_RS2_USE = zz_175; + assign execute_RS2_USE = zz_174; + assign writeBack_RS1 = zz_173; + assign memory_RS1 = zz_172; + assign decode_RS1 = zz_37; + assign decode_BYPASSABLE_EXECUTE_STAGE = zz_44; + assign memory_MEMORY_READ_DATA = zz_54; + assign writeBack_FORMAL_MEM_WDATA = zz_168; + assign memory_FORMAL_MEM_WDATA = zz_167; + assign execute_FORMAL_MEM_WDATA = zz_55; + assign decode_MEMORY_ENABLE = zz_43; + assign fetch_INSTRUCTION = zz_64; + assign writeBack_RS1_USE = zz_159; + assign memory_RS1_USE = zz_158; + assign execute_RS1_USE = zz_157; + assign writeBack_RS2 = zz_156; + assign memory_RS2 = zz_155; + assign decode_RS2 = zz_36; + assign writeBack_FORMAL_MEM_WMASK = zz_153; + assign memory_FORMAL_MEM_WMASK = zz_152; + assign execute_FORMAL_MEM_WMASK = zz_57; + assign decode_SRC_LESS_UNSIGNED = zz_48; + assign writeBack_FORMAL_HALT = zz_147; + assign memory_FORMAL_HALT = zz_146; + assign execute_FORMAL_HALT = zz_145; + assign decode_FORMAL_HALT = zz_144; + assign fetch_FORMAL_HALT = zz_143; + assign prefetch_FORMAL_HALT = zz_70; + assign writeBack_FORMAL_MEM_RDATA = zz_53; + assign execute_BYPASSABLE_MEMORY_STAGE = zz_141; + assign decode_BYPASSABLE_MEMORY_STAGE = zz_40; + assign decode_ALU_CTRL = zz_12; + assign zz_13 = zz_14; + assign execute_BRANCH_CALC = zz_15; + assign decode_SRC2 = zz_28; + assign decode_SRC_USE_SUB_LESS = zz_45; + assign memory_BRANCH_CALC = zz_139; + assign memory_BRANCH_DO = zz_199; + assign execute_PC = zz_192; + assign execute_RS1 = zz_171; + assign execute_BRANCH_CTRL = zz_16; + assign decode_RS2_USE = zz_42; + assign decode_RS1_USE = zz_41; + assign execute_REGFILE_WRITE_VALID = zz_149; + assign execute_BYPASSABLE_EXECUTE_STAGE = zz_170; + assign memory_REGFILE_WRITE_VALID = zz_150; + assign memory_BYPASSABLE_MEMORY_STAGE = zz_142; + assign writeBack_REGFILE_WRITE_VALID = zz_151; + assign memory_SHIFT_RIGHT = zz_187; + always @ (memory_REGFILE_WRITE_DATA or memory_SHIFT_CTRL or zz_122 or memory_SHIFT_RIGHT) begin - decode_arbitration_haltItself = _58; - if(decodeExceptionPort_valid)begin - decode_arbitration_haltItself = _57; - end - if((decode_arbitration_isValid && (_182 || _183)))begin - decode_arbitration_haltItself = _209; - end + zz_18 = memory_REGFILE_WRITE_DATA; + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequancial_SLL_1 : begin + zz_18 = zz_122; + end + `ShiftCtrlEnum_binary_sequancial_SRL_1, `ShiftCtrlEnum_binary_sequancial_SRA_1 : begin + zz_18 = memory_SHIFT_RIGHT; + end + default : begin + end + endcase end - always @ (decode_arbitration_isFlushed or _265 or _266) + assign memory_SHIFT_CTRL = zz_19; + assign execute_SHIFT_CTRL = zz_21; + assign execute_SRC_LESS_UNSIGNED = zz_148; + assign execute_SRC_USE_SUB_LESS = zz_137; + assign zz_25 = decode_PC; + assign zz_26 = decode_RS2; + assign decode_SRC2_CTRL = zz_27; + assign zz_29 = decode_RS1; + assign decode_SRC1_CTRL = zz_30; + assign execute_SRC_ADD_SUB = zz_24; + assign execute_SRC_LESS = zz_22; + assign execute_ALU_CTRL = zz_32; + assign execute_SRC2 = zz_138; + assign execute_SRC1 = zz_179; + assign execute_ALU_BITWISE_CTRL = zz_34; + always @ (writeBack_RegFilePlugin_regFileWrite_valid) begin - decode_arbitration_removeIt = _266; - if(decode_arbitration_isFlushed)begin - decode_arbitration_removeIt = _265; + zz_35 = 1'b0; + if(writeBack_RegFilePlugin_regFileWrite_valid)begin + zz_35 = 1'b1; end end - always @ (execute_arbitration_isValid or dBus_cmd_ready or execute_MEMORY_ENABLE or execute_ALIGNEMENT_FAULT or _93 or _94) + assign decode_INSTRUCTION_ANTICIPATED = zz_63; + always @ (zz_39 or decode_INSTRUCTION) begin - execute_arbitration_haltItself = _94; - if((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_ALIGNEMENT_FAULT)))begin - execute_arbitration_haltItself = _93; + decode_REGFILE_WRITE_VALID = zz_39; + if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin + decode_REGFILE_WRITE_VALID = 1'b0; end end - always @ (execute_arbitration_isFlushed or _267 or _268) + assign decode_LEGAL_INSTRUCTION = zz_52; + assign decode_INSTRUCTION_READY = zz_61; + assign writeBack_MEMORY_ENABLE = zz_166; + assign writeBack_MEMORY_ADDRESS_LOW = zz_189; + assign writeBack_MEMORY_READ_DATA = zz_169; + assign memory_INSTRUCTION = zz_162; + assign memory_MEMORY_ENABLE = zz_165; + assign execute_RS2 = zz_154; + assign execute_SRC_ADD = zz_23; + assign execute_INSTRUCTION = zz_161; + assign execute_ALIGNEMENT_FAULT = zz_60; + assign execute_MEMORY_ENABLE = zz_164; + assign zz_62 = fetch_INSTRUCTION; + assign zz_65 = prefetch_PC; + always @ (memory_FORMAL_PC_NEXT or zz_81 or zz_82) begin - execute_arbitration_removeIt = _268; - if(execute_arbitration_isFlushed)begin - execute_arbitration_removeIt = _267; + zz_66 = memory_FORMAL_PC_NEXT; + if(zz_81)begin + zz_66 = zz_82; end end - always @ (_7 or _243 or _244) + assign prefetch_PC = zz_68; + assign prefetch_PC_CALC_WITHOUT_JUMP = zz_69; + always @ (memory_FORMAL_HALT or memory_arbitration_isValid or memory_BRANCH_DO or zz_82 or memory_MEMORY_ENABLE or memory_INSTRUCTION or dBus_rsp_ready) begin - execute_arbitration_flushAll = _244; - if(_7)begin - execute_arbitration_flushAll = _243; + zz_71 = memory_FORMAL_HALT; + memory_arbitration_haltItself = 1'b0; + if(((memory_arbitration_isValid && memory_BRANCH_DO) && (zz_82[1 : 0] != (2'b00))))begin + zz_71 = 1'b1; + memory_arbitration_haltItself = 1'b1; + end + if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_INSTRUCTION[5])) && (! dBus_rsp_ready)))begin + memory_arbitration_haltItself = 1'b1; end end - always @ (memory_arbitration_isValid or _9 or _60 or _61 or dBus_rsp_ready or memory_MEMORY_ENABLE or memory_INSTRUCTION or _101) + assign zz_72 = execute_FORMAL_HALT; + always @ (decode_FORMAL_HALT or decodeExceptionPort_valid or decode_arbitration_isValid or zz_123 or zz_124) begin - memory_arbitration_haltItself = _61; - if(_9)begin - memory_arbitration_haltItself = _60; + zz_73 = decode_FORMAL_HALT; + decode_arbitration_haltItself = 1'b0; + if(decodeExceptionPort_valid)begin + zz_73 = 1'b1; + decode_arbitration_haltItself = 1'b1; end - if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_INSTRUCTION[5])) && (! dBus_rsp_ready)))begin - memory_arbitration_haltItself = _101; + if((decode_arbitration_isValid && (zz_123 || zz_124)))begin + decode_arbitration_haltItself = 1'b1; end end - always @ (memory_arbitration_isFlushed or _269 or _270) + assign zz_74 = fetch_FORMAL_HALT; + assign zz_75 = prefetch_FORMAL_HALT; + always @ (writeBack_REGFILE_WRITE_DATA or writeBack_arbitration_isValid or writeBack_MEMORY_ENABLE or writeBack_DBusSimplePlugin_rspFormated) begin - memory_arbitration_removeIt = _270; - if(memory_arbitration_isFlushed)begin - memory_arbitration_removeIt = _269; + zz_76 = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + zz_76 = writeBack_DBusSimplePlugin_rspFormated; end end - always @ (writeBack_arbitration_isFlushed or _271 or _272) + assign zz_77 = writeBack_REGFILE_WRITE_VALID; + assign zz_78 = writeBack_RS2_USE; + assign zz_79 = writeBack_RS1_USE; + assign zz_80 = writeBack_INSTRUCTION; + assign writeBack_PC = zz_194; + assign writeBack_INSTRUCTION = zz_163; + assign decode_PC = zz_191; + assign decode_INSTRUCTION = zz_160; + always @ (iBus_cmd_ready or prefetch_IBusSimplePlugin_pendingCmd or iBus_rsp_ready) begin - writeBack_arbitration_removeIt = _272; - if(writeBack_arbitration_isFlushed)begin - writeBack_arbitration_removeIt = _271; + prefetch_arbitration_haltItself = 1'b0; + if(((! iBus_cmd_ready) || (prefetch_IBusSimplePlugin_pendingCmd && (! iBus_rsp_ready))))begin + prefetch_arbitration_haltItself = 1'b1; end end - always @ (_12 or _48 or _50) + assign prefetch_arbitration_haltByOther = 1'b0; + assign prefetch_arbitration_removeIt = 1'b0; + assign prefetch_arbitration_flushAll = 1'b0; + always @ (fetch_arbitration_isValid or iBus_rsp_ready or zz_89) begin - rvfi_trap = _12; - if(_48)begin - rvfi_trap = _50; + fetch_arbitration_haltItself = 1'b0; + if(((fetch_arbitration_isValid && (! iBus_rsp_ready)) && (! zz_89)))begin + fetch_arbitration_haltItself = 1'b1; end end - always @ (writeBack_arbitration_isValid or writeBack_DBusSimplePlugin_rspFormated or writeBack_MEMORY_ENABLE or writeBack_REGFILE_WRITE_DATA) + assign fetch_arbitration_haltByOther = 1'b0; + always @ (fetch_arbitration_isFlushed) begin - _24 = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _24 = writeBack_DBusSimplePlugin_rspFormated; + fetch_arbitration_removeIt = 1'b0; + if(fetch_arbitration_isFlushed)begin + fetch_arbitration_removeIt = 1'b1; end end - always @ (prefetch_arbitration_isValid or fetch_arbitration_isValid or decode_arbitration_isValid or execute_arbitration_isValid or memory_arbitration_isValid or writeBack_arbitration_isValid or _25 or _26 or _27 or _28 or _29 or _30 or _31 or _32 or _33 or _34 or _35 or _36 or _37 or _38 or _39 or _40 or _41 or _42 or writeBack_FORMAL_HALT) + assign fetch_arbitration_flushAll = 1'b0; + assign decode_arbitration_haltByOther = 1'b0; + always @ (decode_arbitration_isFlushed) begin - writeBack_FomalPlugin_haltRequest = _28; - if((prefetch_arbitration_isValid && _25))begin - if((((((_26 && (! fetch_arbitration_isValid)) && (! decode_arbitration_isValid)) && (! execute_arbitration_isValid)) && (! memory_arbitration_isValid)) && (! writeBack_arbitration_isValid)))begin - writeBack_FomalPlugin_haltRequest = _27; - end - end - if((fetch_arbitration_isValid && _29))begin - if(((((_30 && (! decode_arbitration_isValid)) && (! execute_arbitration_isValid)) && (! memory_arbitration_isValid)) && (! writeBack_arbitration_isValid)))begin - writeBack_FomalPlugin_haltRequest = _31; - end - end - if((decode_arbitration_isValid && _32))begin - if((((_33 && (! execute_arbitration_isValid)) && (! memory_arbitration_isValid)) && (! writeBack_arbitration_isValid)))begin - writeBack_FomalPlugin_haltRequest = _34; - end + decode_arbitration_removeIt = 1'b0; + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; end - if((execute_arbitration_isValid && _35))begin - if(((_36 && (! memory_arbitration_isValid)) && (! writeBack_arbitration_isValid)))begin - writeBack_FomalPlugin_haltRequest = _37; - end + end + + assign decode_arbitration_flushAll = 1'b0; + always @ (execute_arbitration_isValid or execute_MEMORY_ENABLE or dBus_cmd_ready or execute_ALIGNEMENT_FAULT) + begin + execute_arbitration_haltItself = 1'b0; + if((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_ALIGNEMENT_FAULT)))begin + execute_arbitration_haltItself = 1'b1; end - if((memory_arbitration_isValid && _38))begin - if((_39 && (! writeBack_arbitration_isValid)))begin - writeBack_FomalPlugin_haltRequest = _40; - end + end + + assign execute_arbitration_haltByOther = 1'b0; + always @ (execute_arbitration_isFlushed) + begin + execute_arbitration_removeIt = 1'b0; + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; end - if((writeBack_arbitration_isValid && writeBack_FORMAL_HALT))begin - if(_41)begin - writeBack_FomalPlugin_haltRequest = _42; - end + end + + always @ (zz_81) + begin + execute_arbitration_flushAll = 1'b0; + if(zz_81)begin + execute_arbitration_flushAll = 1'b1; end end - always @ (decodeExceptionPort_valid or _56 or decode_FORMAL_HALT) + assign memory_arbitration_haltByOther = 1'b0; + always @ (memory_arbitration_isFlushed) begin - _32 = decode_FORMAL_HALT; - if(decodeExceptionPort_valid)begin - _32 = _56; + memory_arbitration_removeIt = 1'b0; + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; end end - always @ (_9 or _59 or memory_FORMAL_HALT) + assign memory_arbitration_flushAll = 1'b0; + assign writeBack_arbitration_haltItself = 1'b0; + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (writeBack_arbitration_isFlushed) begin - _38 = memory_FORMAL_HALT; - if(_9)begin - _38 = _59; + writeBack_arbitration_removeIt = 1'b0; + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; end end - always @ (prefetch_PC_CALC_WITHOUT_JUMP or prefetch_PcManagerSimplePlugin_jump_pcLoad_valid or prefetch_PcManagerSimplePlugin_jump_pcLoad_payload) + assign writeBack_arbitration_flushAll = 1'b0; + always @ (writeBack_arbitration_isFiring or zz_88 or writeBack_FomalPlugin_haltFired) begin - prefetch_PcManagerSimplePlugin_pc = prefetch_PC_CALC_WITHOUT_JUMP; - if(prefetch_PcManagerSimplePlugin_jump_pcLoad_valid)begin - prefetch_PcManagerSimplePlugin_pc = prefetch_PcManagerSimplePlugin_jump_pcLoad_payload; + zz_204 = writeBack_arbitration_isFiring; + rvfi_trap = 1'b0; + zz_205 = 1'b0; + if(zz_88)begin + zz_204 = 1'b1; + rvfi_trap = 1'b1; + zz_205 = 1'b1; + end + if(writeBack_FomalPlugin_haltFired)begin + zz_204 = 1'b0; end end - always @ (prefetch_arbitration_isFiring or prefetch_PcManagerSimplePlugin_jump_pcLoad_valid or _67 or _68 or _70) + assign rvfi_order = writeBack_FomalPlugin_order; + assign rvfi_insn = zz_80; + assign rvfi_intr = 1'b0; + assign rvfi_rs1_addr = (zz_79 ? zz_80[19 : 15] : (5'b00000)); + assign rvfi_rs2_addr = (zz_78 ? zz_80[24 : 20] : (5'b00000)); + assign rvfi_rs1_rdata = (zz_79 ? writeBack_RS1 : (32'b00000000000000000000000000000000)); + assign rvfi_rs2_rdata = (zz_78 ? writeBack_RS2 : (32'b00000000000000000000000000000000)); + assign rvfi_rd_addr = (zz_77 ? zz_80[11 : 7] : (5'b00000)); + assign rvfi_rd_wdata = (zz_77 ? zz_76 : (32'b00000000000000000000000000000000)); + assign rvfi_pc_rdata = writeBack_PC; + assign rvfi_pc_wdata = writeBack_FORMAL_PC_NEXT; + assign rvfi_mem_addr = writeBack_FORMAL_MEM_ADDR; + assign rvfi_mem_rmask = writeBack_FORMAL_MEM_RMASK; + assign rvfi_mem_wmask = writeBack_FORMAL_MEM_WMASK; + assign rvfi_mem_rdata = writeBack_FORMAL_MEM_RDATA; + assign rvfi_mem_wdata = writeBack_FORMAL_MEM_WDATA; + always @ (prefetch_arbitration_isValid or zz_75 or fetch_arbitration_isValid or decode_arbitration_isValid or execute_arbitration_isValid or memory_arbitration_isValid or writeBack_arbitration_isValid or zz_74 or zz_73 or zz_72 or zz_71 or writeBack_FORMAL_HALT) begin - prefetch_PcManagerSimplePlugin_samplePcNext = _68; - if(prefetch_PcManagerSimplePlugin_jump_pcLoad_valid)begin - prefetch_PcManagerSimplePlugin_samplePcNext = _67; + writeBack_FomalPlugin_haltRequest = 1'b0; + if((prefetch_arbitration_isValid && zz_75))begin + if((((((1'b1 && (! fetch_arbitration_isValid)) && (! decode_arbitration_isValid)) && (! execute_arbitration_isValid)) && (! memory_arbitration_isValid)) && (! writeBack_arbitration_isValid)))begin + writeBack_FomalPlugin_haltRequest = 1'b1; + end end - if(prefetch_arbitration_isFiring)begin - prefetch_PcManagerSimplePlugin_samplePcNext = _70; + if((fetch_arbitration_isValid && zz_74))begin + if(((((1'b1 && (! decode_arbitration_isValid)) && (! execute_arbitration_isValid)) && (! memory_arbitration_isValid)) && (! writeBack_arbitration_isValid)))begin + writeBack_FomalPlugin_haltRequest = 1'b1; + end + end + if((decode_arbitration_isValid && zz_73))begin + if((((1'b1 && (! execute_arbitration_isValid)) && (! memory_arbitration_isValid)) && (! writeBack_arbitration_isValid)))begin + writeBack_FomalPlugin_haltRequest = 1'b1; + end + end + if((execute_arbitration_isValid && zz_72))begin + if(((1'b1 && (! memory_arbitration_isValid)) && (! writeBack_arbitration_isValid)))begin + writeBack_FomalPlugin_haltRequest = 1'b1; + end + end + if((memory_arbitration_isValid && zz_71))begin + if((1'b1 && (! writeBack_arbitration_isValid)))begin + writeBack_FomalPlugin_haltRequest = 1'b1; + end + end + if((writeBack_arbitration_isValid && writeBack_FORMAL_HALT))begin + if(1'b1)begin + writeBack_FomalPlugin_haltRequest = 1'b1; + end end end - always @ (_7 or _8 or memory_FORMAL_PC_NEXT) + assign zz_83 = 1'b0; + assign zz_70 = 1'b0; + assign prefetch_PcManagerSimplePlugin_pcBeforeJumps = (prefetch_PcManagerSimplePlugin_pcReg + zz_213); + assign zz_69 = prefetch_PcManagerSimplePlugin_pcBeforeJumps; + always @ (prefetch_PC_CALC_WITHOUT_JUMP or prefetch_PcManagerSimplePlugin_jump_pcLoad_valid or prefetch_PcManagerSimplePlugin_jump_pcLoad_payload or prefetch_arbitration_isFiring) begin - _72 = memory_FORMAL_PC_NEXT; - if(_7)begin - _72 = _8; + prefetch_PcManagerSimplePlugin_pc = prefetch_PC_CALC_WITHOUT_JUMP; + prefetch_PcManagerSimplePlugin_samplePcNext = 1'b0; + if(prefetch_PcManagerSimplePlugin_jump_pcLoad_valid)begin + prefetch_PcManagerSimplePlugin_samplePcNext = 1'b1; + prefetch_PcManagerSimplePlugin_pc = prefetch_PcManagerSimplePlugin_jump_pcLoad_payload; + end + if(prefetch_arbitration_isFiring)begin + prefetch_PcManagerSimplePlugin_samplePcNext = 1'b1; end end - always @ (iBus_rsp_inst or _80 or _83) + assign prefetch_PcManagerSimplePlugin_jump_pcLoad_valid = zz_81; + assign prefetch_PcManagerSimplePlugin_jump_pcLoad_payload = zz_82; + assign zz_68 = prefetch_PcManagerSimplePlugin_pc; + assign zz_67 = (prefetch_PC + (32'b00000000000000000000000000000100)); + assign zz_206 = (((prefetch_arbitration_isValid && (! prefetch_arbitration_removeIt)) && (! prefetch_arbitration_isStuckByOthers)) && (! (prefetch_IBusSimplePlugin_pendingCmd && (! iBus_rsp_ready)))); + assign iBus_cmd_payload_pc = zz_65; + always @ (iBus_rsp_inst or zz_89 or zz_90) begin - _84 = iBus_rsp_inst; - if(_80)begin - _84 = _83; + zz_64 = iBus_rsp_inst; + if(zz_89)begin + zz_64 = zz_90; end end - always @ (execute_RS2 or _288) + assign zz_63 = (decode_arbitration_isStuck ? decode_INSTRUCTION : zz_62); + assign zz_61 = 1'b1; + assign zz_60 = 1'b0; + assign zz_209 = ((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_removeIt)) && (! execute_ALIGNEMENT_FAULT)); + assign zz_210 = execute_INSTRUCTION[5]; + assign zz_208 = execute_SRC_ADD; + assign zz_207 = execute_INSTRUCTION[13 : 12]; + always @ (zz_207 or execute_RS2) begin - case(_288) - (2'b00) : begin - _92 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + case(zz_207) + 2'b00 : begin + zz_91 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end - (2'b01) : begin - _92 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + 2'b01 : begin + zz_91 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _92 = execute_RS2[31 : 0]; + zz_91 = execute_RS2[31 : 0]; end endcase end - always @ (_96 or _97 or _98 or _288) + assign zz_211 = zz_91; + assign zz_59 = zz_208[1 : 0]; + always @ (zz_207) begin - case(_288) - (2'b00) : begin - execute_DBusSimplePlugin_formalMask = _96; + case(zz_207) + 2'b00 : begin + execute_DBusSimplePlugin_formalMask = (4'b0001); end - (2'b01) : begin - execute_DBusSimplePlugin_formalMask = _97; + 2'b01 : begin + execute_DBusSimplePlugin_formalMask = (4'b0011); end default : begin - execute_DBusSimplePlugin_formalMask = _98; + execute_DBusSimplePlugin_formalMask = (4'b1111); end endcase end + assign zz_58 = zz_208; + assign zz_57 = ((zz_209 && zz_210) ? execute_DBusSimplePlugin_formalMask : (4'b0000)); + assign zz_56 = ((zz_209 && (! zz_210)) ? execute_DBusSimplePlugin_formalMask : (4'b0000)); + assign zz_55 = zz_211; + assign zz_54 = dBus_rsp_data; always @ (writeBack_MEMORY_READ_DATA or writeBack_MEMORY_ADDRESS_LOW) begin writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; case(writeBack_MEMORY_ADDRESS_LOW) - (2'b01) : begin + 2'b01 : begin writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8]; end - (2'b10) : begin + 2'b10 : begin writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16]; end - (2'b11) : begin + 2'b11 : begin writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24]; end default : begin @@ -1197,64 +999,66 @@ module VexRiscv endcase end - always @ (writeBack_DBusSimplePlugin_rspShifted or _106) + assign zz_92 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (zz_92 or writeBack_DBusSimplePlugin_rspShifted) begin - _107[31] = _106; - _107[30] = _106; - _107[29] = _106; - _107[28] = _106; - _107[27] = _106; - _107[26] = _106; - _107[25] = _106; - _107[24] = _106; - _107[23] = _106; - _107[22] = _106; - _107[21] = _106; - _107[20] = _106; - _107[19] = _106; - _107[18] = _106; - _107[17] = _106; - _107[16] = _106; - _107[15] = _106; - _107[14] = _106; - _107[13] = _106; - _107[12] = _106; - _107[11] = _106; - _107[10] = _106; - _107[9] = _106; - _107[8] = _106; - _107[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + zz_93[31] = zz_92; + zz_93[30] = zz_92; + zz_93[29] = zz_92; + zz_93[28] = zz_92; + zz_93[27] = zz_92; + zz_93[26] = zz_92; + zz_93[25] = zz_92; + zz_93[24] = zz_92; + zz_93[23] = zz_92; + zz_93[22] = zz_92; + zz_93[21] = zz_92; + zz_93[20] = zz_92; + zz_93[19] = zz_92; + zz_93[18] = zz_92; + zz_93[17] = zz_92; + zz_93[16] = zz_92; + zz_93[15] = zz_92; + zz_93[14] = zz_92; + zz_93[13] = zz_92; + zz_93[12] = zz_92; + zz_93[11] = zz_92; + zz_93[10] = zz_92; + zz_93[9] = zz_92; + zz_93[8] = zz_92; + zz_93[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; end - always @ (writeBack_DBusSimplePlugin_rspShifted or _108) + assign zz_94 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (zz_94 or writeBack_DBusSimplePlugin_rspShifted) begin - _109[31] = _108; - _109[30] = _108; - _109[29] = _108; - _109[28] = _108; - _109[27] = _108; - _109[26] = _108; - _109[25] = _108; - _109[24] = _108; - _109[23] = _108; - _109[22] = _108; - _109[21] = _108; - _109[20] = _108; - _109[19] = _108; - _109[18] = _108; - _109[17] = _108; - _109[16] = _108; - _109[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + zz_95[31] = zz_94; + zz_95[30] = zz_94; + zz_95[29] = zz_94; + zz_95[28] = zz_94; + zz_95[27] = zz_94; + zz_95[26] = zz_94; + zz_95[25] = zz_94; + zz_95[24] = zz_94; + zz_95[23] = zz_94; + zz_95[22] = zz_94; + zz_95[21] = zz_94; + zz_95[20] = zz_94; + zz_95[19] = zz_94; + zz_95[18] = zz_94; + zz_95[17] = zz_94; + zz_95[16] = zz_94; + zz_95[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; end - always @ (writeBack_DBusSimplePlugin_rspShifted or _105 or _107 or _109) + always @ (zz_212 or zz_93 or zz_95 or writeBack_DBusSimplePlugin_rspShifted) begin - case(_105) - (2'b00) : begin - writeBack_DBusSimplePlugin_rspFormated = _107; + case(zz_212) + 2'b00 : begin + writeBack_DBusSimplePlugin_rspFormated = zz_93; end - (2'b01) : begin - writeBack_DBusSimplePlugin_rspFormated = _109; + 2'b01 : begin + writeBack_DBusSimplePlugin_rspFormated = zz_95; end default : begin writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; @@ -1262,22 +1066,58 @@ module VexRiscv endcase end - always @ (decode_INSTRUCTION or _131 or _133) - begin - decode_REGFILE_WRITE_VALID = _131[0]; - if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin - decode_REGFILE_WRITE_VALID = _133; - end - end - - always @ (writeBack_arbitration_isFiring or _21 or _138 or _140) + assign zz_53 = writeBack_DBusSimplePlugin_rspFormated; + assign zz_97 = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000000000)); + assign zz_98 = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); + assign zz_99 = ((decode_INSTRUCTION & (32'b00000000000000000000000000001000)) == (32'b00000000000000000000000000001000)); + assign zz_100 = ((decode_INSTRUCTION & (32'b00000000000000000000000001110000)) == (32'b00000000000000000000000000100000)); + assign zz_101 = ((decode_INSTRUCTION & (32'b00000000000000000000000000010100)) == (32'b00000000000000000000000000000100)); + assign zz_102 = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000001000000)); + assign zz_103 = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000000000)); + assign zz_104 = ((decode_INSTRUCTION & (32'b00000000000000000000000000010000)) == (32'b00000000000000000000000000010000)); + assign zz_96 = {({zz_99,zz_101} != (2'b00)),{(((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000100)) != (1'b0)),{({zz_99,{zz_104,{zz_98,{zz_97,((decode_INSTRUCTION & (32'b00000000000000000100000001000000)) == (32'b00000000000000000100000000000000))}}}} != (5'b00000)),{({zz_104,((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000100000))} != (2'b00)),{({((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000000)),{zz_103,((decode_INSTRUCTION & (32'b00000000000000000000000000011000)) == (32'b00000000000000000000000000000000))}} != (3'b000)),{({zz_102,{((decode_INSTRUCTION & (32'b00000000000000000000000000100100)) == (32'b00000000000000000000000000100000)),zz_100}} != (3'b000)),{(zz_103 != (1'b0)),{({zz_98,{((decode_INSTRUCTION & (32'b00000000000000000010000000100000)) == (32'b00000000000000000010000000100000)),{((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000010000)),{((decode_INSTRUCTION & (32'b00000000000000000001000000100000)) == (32'b00000000000000000000000000100000)),((decode_INSTRUCTION & (32'b00000000000000000001000000010000)) == (32'b00000000000000000000000000010000))}}}} != (5'b00000)),{({zz_102,{((decode_INSTRUCTION & (32'b01000000000000000000000000110000)) == (32'b01000000000000000000000000110000)),((decode_INSTRUCTION & (32'b00000000000000000010000000010100)) == (32'b00000000000000000010000000010000))}} != (3'b000)),{({((decode_INSTRUCTION & (32'b00000000000000000111000000010100)) == (32'b00000000000000000101000000010000)),((decode_INSTRUCTION & (32'b00000000000000000111000001100100)) == (32'b00000000000000000101000000100000))} != (2'b00)),{({((decode_INSTRUCTION & (32'b01000000000000000011000000010100)) == (32'b01000000000000000001000000010000)),{((decode_INSTRUCTION & (32'b01000000000000000100000001100100)) == (32'b01000000000000000100000000100000)),((decode_INSTRUCTION & (32'b00000000000000000111000000010100)) == (32'b00000000000000000001000000010000))}} != (3'b000)),{({((decode_INSTRUCTION & (32'b00000000000000000100000000000100)) == (32'b00000000000000000100000000000000)),((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100100))} != (2'b00)),{(((decode_INSTRUCTION & (32'b00000000000000000110000000000100)) == (32'b00000000000000000010000000000000)) != (1'b0)),{({((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000000000)),((decode_INSTRUCTION & (32'b00000000000000000101000000000000)) == (32'b00000000000000000001000000000000))} != (2'b00)),{({zz_99,zz_101} != (2'b00)),{(((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001000000)) != (1'b0)),{({((decode_INSTRUCTION & (32'b00000000000000000001000000000000)) == (32'b00000000000000000001000000000000)),zz_98} != (2'b00)),{({zz_98,((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000010000000000000))} != (2'b00)),{({zz_99,{zz_98,zz_100}} != (3'b000)),({zz_99,{zz_98,zz_97}} != (3'b000))}}}}}}}}}}}}}}}}}}}; + assign zz_52 = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000001100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)),{((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & (32'b00000000000000000110000001011111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & (32'b00000000000000000101000001011111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & (32'b00000000000000000111000001111011)) == (32'b00000000000000000000000001100011)),{((decode_INSTRUCTION & (32'b11111110000000000000000001111111)) == (32'b00000000000000000000000000110011)),{((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & (32'b11111100000000000011000001111111)) == (32'b00000000000000000001000000010011)),{((decode_INSTRUCTION & (32'b10111110000000000111000001111111)) == (32'b00000000000000000101000000110011)),((decode_INSTRUCTION & (32'b10111110000000000111000001111111)) == (32'b00000000000000000000000000110011))}}}}}}}}}}}}}}} != (16'b0000000000000000)); + assign zz_105 = zz_96[1 : 0]; + assign zz_51 = zz_105; + assign zz_106 = zz_96[3 : 2]; + assign zz_50 = zz_106; + assign zz_107 = zz_96[5 : 4]; + assign zz_49 = zz_107; + assign zz_48 = zz_214[0]; + assign zz_108 = zz_96[8 : 7]; + assign zz_47 = zz_108; + assign zz_109 = zz_96[10 : 9]; + assign zz_46 = zz_109; + assign zz_45 = zz_215[0]; + assign zz_44 = zz_216[0]; + assign zz_43 = zz_217[0]; + assign zz_42 = zz_218[0]; + assign zz_41 = zz_219[0]; + assign zz_40 = zz_220[0]; + assign zz_39 = zz_221[0]; + assign zz_110 = zz_96[19 : 18]; + assign zz_38 = zz_110; + assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = (4'b0010); + assign decodeExceptionPort_payload_badAddr = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign zz_111 = 1'b1; + assign decode_RegFilePlugin_rs1Data = zz_202; + assign zz_112 = 1'b1; + assign decode_RegFilePlugin_rs2Data = zz_203; + assign zz_37 = decode_RegFilePlugin_rs1Data; + assign zz_36 = decode_RegFilePlugin_rs2Data; + always @ (zz_77 or writeBack_arbitration_isFiring or zz_113) begin - writeBack_RegFilePlugin_regFileWrite_valid = (_21 && writeBack_arbitration_isFiring); - if(_138)begin - writeBack_RegFilePlugin_regFileWrite_valid = _140; + writeBack_RegFilePlugin_regFileWrite_valid = (zz_77 && writeBack_arbitration_isFiring); + if(zz_113)begin + writeBack_RegFilePlugin_regFileWrite_valid = 1'b1; end end + assign writeBack_RegFilePlugin_regFileWrite_payload_address = zz_80[11 : 7]; + assign writeBack_RegFilePlugin_regFileWrite_payload_data = zz_76; always @ (execute_ALU_BITWISE_CTRL or execute_SRC1 or execute_SRC2) begin case(execute_ALU_BITWISE_CTRL) @@ -1296,688 +1136,702 @@ module VexRiscv endcase end - always @ (execute_IntAluPlugin_bitwise or execute_ALU_CTRL or _144 or execute_SRC_ADD_SUB) + always @ (execute_ALU_CTRL or execute_IntAluPlugin_bitwise or execute_SRC_LESS or execute_SRC_ADD_SUB) begin case(execute_ALU_CTRL) `AluCtrlEnum_binary_sequancial_BITWISE : begin - _145 = execute_IntAluPlugin_bitwise; + zz_114 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_binary_sequancial_SLT_SLTU : begin - _145 = _144; + zz_114 = {31'd0, execute_SRC_LESS}; end default : begin - _145 = execute_SRC_ADD_SUB; + zz_114 = execute_SRC_ADD_SUB; end endcase end - always @ (decode_INSTRUCTION or decode_SRC1_CTRL or _148 or _149) + assign zz_33 = zz_114; + always @ (decode_SRC1_CTRL or zz_29 or decode_INSTRUCTION) begin case(decode_SRC1_CTRL) `Src1CtrlEnum_binary_sequancial_RS : begin - _150 = _148; + zz_115 = zz_29; end `Src1CtrlEnum_binary_sequancial_FOUR : begin - _150 = (32'b00000000000000000000000000000100); + zz_115 = (32'b00000000000000000000000000000100); end default : begin - _150 = {decode_INSTRUCTION[31 : 12],_149}; + zz_115 = {decode_INSTRUCTION[31 : 12],(12'b000000000000)}; end endcase end - always @ (_155) + assign zz_31 = zz_115; + assign zz_116 = zz_222[11]; + always @ (zz_116) begin - _156[19] = _155; - _156[18] = _155; - _156[17] = _155; - _156[16] = _155; - _156[15] = _155; - _156[14] = _155; - _156[13] = _155; - _156[12] = _155; - _156[11] = _155; - _156[10] = _155; - _156[9] = _155; - _156[8] = _155; - _156[7] = _155; - _156[6] = _155; - _156[5] = _155; - _156[4] = _155; - _156[3] = _155; - _156[2] = _155; - _156[1] = _155; - _156[0] = _155; + zz_117[19] = zz_116; + zz_117[18] = zz_116; + zz_117[17] = zz_116; + zz_117[16] = zz_116; + zz_117[15] = zz_116; + zz_117[14] = zz_116; + zz_117[13] = zz_116; + zz_117[12] = zz_116; + zz_117[11] = zz_116; + zz_117[10] = zz_116; + zz_117[9] = zz_116; + zz_117[8] = zz_116; + zz_117[7] = zz_116; + zz_117[6] = zz_116; + zz_117[5] = zz_116; + zz_117[4] = zz_116; + zz_117[3] = zz_116; + zz_117[2] = zz_116; + zz_117[1] = zz_116; + zz_117[0] = zz_116; end - always @ (_158) + assign zz_118 = zz_223[11]; + always @ (zz_118) begin - _159[19] = _158; - _159[18] = _158; - _159[17] = _158; - _159[16] = _158; - _159[15] = _158; - _159[14] = _158; - _159[13] = _158; - _159[12] = _158; - _159[11] = _158; - _159[10] = _158; - _159[9] = _158; - _159[8] = _158; - _159[7] = _158; - _159[6] = _158; - _159[5] = _158; - _159[4] = _158; - _159[3] = _158; - _159[2] = _158; - _159[1] = _158; - _159[0] = _158; + zz_119[19] = zz_118; + zz_119[18] = zz_118; + zz_119[17] = zz_118; + zz_119[16] = zz_118; + zz_119[15] = zz_118; + zz_119[14] = zz_118; + zz_119[13] = zz_118; + zz_119[12] = zz_118; + zz_119[11] = zz_118; + zz_119[10] = zz_118; + zz_119[9] = zz_118; + zz_119[8] = zz_118; + zz_119[7] = zz_118; + zz_119[6] = zz_118; + zz_119[5] = zz_118; + zz_119[4] = zz_118; + zz_119[3] = zz_118; + zz_119[2] = zz_118; + zz_119[1] = zz_118; + zz_119[0] = zz_118; end - always @ (decode_INSTRUCTION or decode_SRC2_CTRL or _153 or _156 or _159 or _160) + always @ (decode_SRC2_CTRL or zz_26 or zz_117 or decode_INSTRUCTION or zz_119 or zz_25) begin case(decode_SRC2_CTRL) `Src2CtrlEnum_binary_sequancial_RS : begin - _161 = _153; + zz_120 = zz_26; end `Src2CtrlEnum_binary_sequancial_IMI : begin - _161 = {_156,decode_INSTRUCTION[31 : 20]}; + zz_120 = {zz_117,decode_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_binary_sequancial_IMS : begin - _161 = {_159,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}}; + zz_120 = {zz_119,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}}; end default : begin - _161 = _160; + zz_120 = zz_25; end endcase end + assign zz_28 = zz_120; + assign execute_SrcPlugin_addSub = zz_224; + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign zz_24 = execute_SrcPlugin_addSub; + assign zz_23 = execute_SrcPlugin_addSub; + assign zz_22 = execute_SrcPlugin_less; + assign execute_FullBarrielShifterPlugin_amplitude = execute_SRC2[4 : 0]; always @ (execute_SRC1) begin - _172[0] = execute_SRC1[31]; - _172[1] = execute_SRC1[30]; - _172[2] = execute_SRC1[29]; - _172[3] = execute_SRC1[28]; - _172[4] = execute_SRC1[27]; - _172[5] = execute_SRC1[26]; - _172[6] = execute_SRC1[25]; - _172[7] = execute_SRC1[24]; - _172[8] = execute_SRC1[23]; - _172[9] = execute_SRC1[22]; - _172[10] = execute_SRC1[21]; - _172[11] = execute_SRC1[20]; - _172[12] = execute_SRC1[19]; - _172[13] = execute_SRC1[18]; - _172[14] = execute_SRC1[17]; - _172[15] = execute_SRC1[16]; - _172[16] = execute_SRC1[15]; - _172[17] = execute_SRC1[14]; - _172[18] = execute_SRC1[13]; - _172[19] = execute_SRC1[12]; - _172[20] = execute_SRC1[11]; - _172[21] = execute_SRC1[10]; - _172[22] = execute_SRC1[9]; - _172[23] = execute_SRC1[8]; - _172[24] = execute_SRC1[7]; - _172[25] = execute_SRC1[6]; - _172[26] = execute_SRC1[5]; - _172[27] = execute_SRC1[4]; - _172[28] = execute_SRC1[3]; - _172[29] = execute_SRC1[2]; - _172[30] = execute_SRC1[1]; - _172[31] = execute_SRC1[0]; - end - - always @ (memory_SHIFT_CTRL or _177 or memory_SHIFT_RIGHT or _179 or _180 or _181 or memory_REGFILE_WRITE_DATA) - begin - _178 = memory_REGFILE_WRITE_DATA; - if((memory_SHIFT_CTRL == _177))begin - _178 = _179; - end else if(((memory_SHIFT_CTRL == _180) || (memory_SHIFT_CTRL == _181)))begin - _178 = memory_SHIFT_RIGHT; - end + zz_121[0] = execute_SRC1[31]; + zz_121[1] = execute_SRC1[30]; + zz_121[2] = execute_SRC1[29]; + zz_121[3] = execute_SRC1[28]; + zz_121[4] = execute_SRC1[27]; + zz_121[5] = execute_SRC1[26]; + zz_121[6] = execute_SRC1[25]; + zz_121[7] = execute_SRC1[24]; + zz_121[8] = execute_SRC1[23]; + zz_121[9] = execute_SRC1[22]; + zz_121[10] = execute_SRC1[21]; + zz_121[11] = execute_SRC1[20]; + zz_121[12] = execute_SRC1[19]; + zz_121[13] = execute_SRC1[18]; + zz_121[14] = execute_SRC1[17]; + zz_121[15] = execute_SRC1[16]; + zz_121[16] = execute_SRC1[15]; + zz_121[17] = execute_SRC1[14]; + zz_121[18] = execute_SRC1[13]; + zz_121[19] = execute_SRC1[12]; + zz_121[20] = execute_SRC1[11]; + zz_121[21] = execute_SRC1[10]; + zz_121[22] = execute_SRC1[9]; + zz_121[23] = execute_SRC1[8]; + zz_121[24] = execute_SRC1[7]; + zz_121[25] = execute_SRC1[6]; + zz_121[26] = execute_SRC1[5]; + zz_121[27] = execute_SRC1[4]; + zz_121[28] = execute_SRC1[3]; + zz_121[29] = execute_SRC1[2]; + zz_121[30] = execute_SRC1[1]; + zz_121[31] = execute_SRC1[0]; end + assign execute_FullBarrielShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequancial_SLL_1) ? zz_121 : execute_SRC1); + assign zz_20 = zz_233; always @ (memory_SHIFT_RIGHT) begin - _179[0] = memory_SHIFT_RIGHT[31]; - _179[1] = memory_SHIFT_RIGHT[30]; - _179[2] = memory_SHIFT_RIGHT[29]; - _179[3] = memory_SHIFT_RIGHT[28]; - _179[4] = memory_SHIFT_RIGHT[27]; - _179[5] = memory_SHIFT_RIGHT[26]; - _179[6] = memory_SHIFT_RIGHT[25]; - _179[7] = memory_SHIFT_RIGHT[24]; - _179[8] = memory_SHIFT_RIGHT[23]; - _179[9] = memory_SHIFT_RIGHT[22]; - _179[10] = memory_SHIFT_RIGHT[21]; - _179[11] = memory_SHIFT_RIGHT[20]; - _179[12] = memory_SHIFT_RIGHT[19]; - _179[13] = memory_SHIFT_RIGHT[18]; - _179[14] = memory_SHIFT_RIGHT[17]; - _179[15] = memory_SHIFT_RIGHT[16]; - _179[16] = memory_SHIFT_RIGHT[15]; - _179[17] = memory_SHIFT_RIGHT[14]; - _179[18] = memory_SHIFT_RIGHT[13]; - _179[19] = memory_SHIFT_RIGHT[12]; - _179[20] = memory_SHIFT_RIGHT[11]; - _179[21] = memory_SHIFT_RIGHT[10]; - _179[22] = memory_SHIFT_RIGHT[9]; - _179[23] = memory_SHIFT_RIGHT[8]; - _179[24] = memory_SHIFT_RIGHT[7]; - _179[25] = memory_SHIFT_RIGHT[6]; - _179[26] = memory_SHIFT_RIGHT[5]; - _179[27] = memory_SHIFT_RIGHT[4]; - _179[28] = memory_SHIFT_RIGHT[3]; - _179[29] = memory_SHIFT_RIGHT[2]; - _179[30] = memory_SHIFT_RIGHT[1]; - _179[31] = memory_SHIFT_RIGHT[0]; + zz_122[0] = memory_SHIFT_RIGHT[31]; + zz_122[1] = memory_SHIFT_RIGHT[30]; + zz_122[2] = memory_SHIFT_RIGHT[29]; + zz_122[3] = memory_SHIFT_RIGHT[28]; + zz_122[4] = memory_SHIFT_RIGHT[27]; + zz_122[5] = memory_SHIFT_RIGHT[26]; + zz_122[6] = memory_SHIFT_RIGHT[25]; + zz_122[7] = memory_SHIFT_RIGHT[24]; + zz_122[8] = memory_SHIFT_RIGHT[23]; + zz_122[9] = memory_SHIFT_RIGHT[22]; + zz_122[10] = memory_SHIFT_RIGHT[21]; + zz_122[11] = memory_SHIFT_RIGHT[20]; + zz_122[12] = memory_SHIFT_RIGHT[19]; + zz_122[13] = memory_SHIFT_RIGHT[18]; + zz_122[14] = memory_SHIFT_RIGHT[17]; + zz_122[15] = memory_SHIFT_RIGHT[16]; + zz_122[16] = memory_SHIFT_RIGHT[15]; + zz_122[17] = memory_SHIFT_RIGHT[14]; + zz_122[18] = memory_SHIFT_RIGHT[13]; + zz_122[19] = memory_SHIFT_RIGHT[12]; + zz_122[20] = memory_SHIFT_RIGHT[11]; + zz_122[21] = memory_SHIFT_RIGHT[10]; + zz_122[22] = memory_SHIFT_RIGHT[9]; + zz_122[23] = memory_SHIFT_RIGHT[8]; + zz_122[24] = memory_SHIFT_RIGHT[7]; + zz_122[25] = memory_SHIFT_RIGHT[6]; + zz_122[26] = memory_SHIFT_RIGHT[5]; + zz_122[27] = memory_SHIFT_RIGHT[4]; + zz_122[28] = memory_SHIFT_RIGHT[3]; + zz_122[29] = memory_SHIFT_RIGHT[2]; + zz_122[30] = memory_SHIFT_RIGHT[1]; + zz_122[31] = memory_SHIFT_RIGHT[0]; end - always @ (decode_INSTRUCTION or writeBack_INSTRUCTION or execute_INSTRUCTION or memory_INSTRUCTION or _184 or _185 or _187 or _188 or _192 or _194 or _195 or _197 or _199 or _200 or _202 or _204 or _205 or decode_RS1_USE or _207) + always @ (zz_125 or zz_126 or decode_INSTRUCTION or writeBack_arbitration_isValid or writeBack_REGFILE_WRITE_VALID or writeBack_INSTRUCTION or memory_arbitration_isValid or memory_REGFILE_WRITE_VALID or memory_BYPASSABLE_MEMORY_STAGE or memory_INSTRUCTION or execute_arbitration_isValid or execute_REGFILE_WRITE_VALID or execute_BYPASSABLE_EXECUTE_STAGE or execute_INSTRUCTION or decode_RS1_USE or decode_RS2_USE) begin - _182 = _188; - if(_184)begin - if((_185 == decode_INSTRUCTION[19 : 15]))begin - _182 = _187; + zz_123 = 1'b0; + zz_124 = 1'b0; + if(zz_125)begin + if((zz_126 == decode_INSTRUCTION[19 : 15]))begin + zz_123 = 1'b1; end - end - if(_192)begin - if(_194)begin - if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _182 = _195; - end + if((zz_126 == decode_INSTRUCTION[24 : 20]))begin + zz_124 = 1'b1; end end - if(_197)begin - if(_199)begin - if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _182 = _200; - end - end - end - if(_202)begin - if(_204)begin - if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _182 = _205; + if((writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID))begin + if((1'b1 || (! 1'b1)))begin + if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin + zz_123 = 1'b1; end - end - end - if((! decode_RS1_USE))begin - _182 = _207; - end - end - - always @ (decode_INSTRUCTION or writeBack_INSTRUCTION or execute_INSTRUCTION or memory_INSTRUCTION or _184 or _185 or _189 or _190 or _192 or _194 or _196 or _197 or _199 or _201 or _202 or _204 or _206 or decode_RS2_USE or _208) - begin - _183 = _190; - if(_184)begin - if((_185 == decode_INSTRUCTION[24 : 20]))begin - _183 = _189; - end - end - if(_192)begin - if(_194)begin if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _183 = _196; + zz_124 = 1'b1; end end end - if(_197)begin - if(_199)begin + if((memory_arbitration_isValid && memory_REGFILE_WRITE_VALID))begin + if((1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)))begin + if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin + zz_123 = 1'b1; + end if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _183 = _201; + zz_124 = 1'b1; end end end - if(_202)begin - if(_204)begin + if((execute_arbitration_isValid && execute_REGFILE_WRITE_VALID))begin + if((1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)))begin + if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin + zz_123 = 1'b1; + end if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _183 = _206; + zz_124 = 1'b1; end end end + if((! decode_RS1_USE))begin + zz_123 = 1'b0; + end if((! decode_RS2_USE))begin - _183 = _208; + zz_124 = 1'b0; end end - always @ (execute_SRC_LESS or execute_BranchPlugin_eq or _213 or _214 or _215 or _217 or _218) + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign zz_127 = execute_INSTRUCTION[14 : 12]; + always @ (zz_127 or execute_BranchPlugin_eq or execute_SRC_LESS) begin - if((_213 == _214))begin - _216 = execute_BranchPlugin_eq; - end else if((_213 == _215))begin - _216 = (! execute_BranchPlugin_eq); - end else if(((_213 & _217) == _218))begin - _216 = (! execute_SRC_LESS); + if((zz_127 == (3'b000))) begin + zz_128 = execute_BranchPlugin_eq; + end else if((zz_127 == (3'b001))) begin + zz_128 = (! execute_BranchPlugin_eq); + end else if((((zz_127 & (3'b101)) == (3'b101)))) begin + zz_128 = (! execute_SRC_LESS); end else begin - _216 = execute_SRC_LESS; + zz_128 = execute_SRC_LESS; end end - always @ (execute_BRANCH_CTRL or _210 or _211 or _212 or _216) + always @ (execute_BRANCH_CTRL or zz_128) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_binary_sequancial_INC : begin - _219 = _210; + zz_129 = 1'b0; end `BranchCtrlEnum_binary_sequancial_JAL : begin - _219 = _211; + zz_129 = 1'b1; end `BranchCtrlEnum_binary_sequancial_JALR : begin - _219 = _212; + zz_129 = 1'b1; end default : begin - _219 = _216; + zz_129 = zz_128; end endcase end - always @ (_226) + assign zz_17 = zz_129; + assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequancial_JALR) ? execute_RS1 : execute_PC); + assign zz_130 = zz_235[19]; + always @ (zz_130) begin - _227[10] = _226; - _227[9] = _226; - _227[8] = _226; - _227[7] = _226; - _227[6] = _226; - _227[5] = _226; - _227[4] = _226; - _227[3] = _226; - _227[2] = _226; - _227[1] = _226; - _227[0] = _226; + zz_131[10] = zz_130; + zz_131[9] = zz_130; + zz_131[8] = zz_130; + zz_131[7] = zz_130; + zz_131[6] = zz_130; + zz_131[5] = zz_130; + zz_131[4] = zz_130; + zz_131[3] = zz_130; + zz_131[2] = zz_130; + zz_131[1] = zz_130; + zz_131[0] = zz_130; end - always @ (_230) + assign zz_132 = zz_236[11]; + always @ (zz_132) begin - _231[19] = _230; - _231[18] = _230; - _231[17] = _230; - _231[16] = _230; - _231[15] = _230; - _231[14] = _230; - _231[13] = _230; - _231[12] = _230; - _231[11] = _230; - _231[10] = _230; - _231[9] = _230; - _231[8] = _230; - _231[7] = _230; - _231[6] = _230; - _231[5] = _230; - _231[4] = _230; - _231[3] = _230; - _231[2] = _230; - _231[1] = _230; - _231[0] = _230; + zz_133[19] = zz_132; + zz_133[18] = zz_132; + zz_133[17] = zz_132; + zz_133[16] = zz_132; + zz_133[15] = zz_132; + zz_133[14] = zz_132; + zz_133[13] = zz_132; + zz_133[12] = zz_132; + zz_133[11] = zz_132; + zz_133[10] = zz_132; + zz_133[9] = zz_132; + zz_133[8] = zz_132; + zz_133[7] = zz_132; + zz_133[6] = zz_132; + zz_133[5] = zz_132; + zz_133[4] = zz_132; + zz_133[3] = zz_132; + zz_133[2] = zz_132; + zz_133[1] = zz_132; + zz_133[0] = zz_132; end - always @ (_233) + assign zz_134 = zz_237[11]; + always @ (zz_134) begin - _234[18] = _233; - _234[17] = _233; - _234[16] = _233; - _234[15] = _233; - _234[14] = _233; - _234[13] = _233; - _234[12] = _233; - _234[11] = _233; - _234[10] = _233; - _234[9] = _233; - _234[8] = _233; - _234[7] = _233; - _234[6] = _233; - _234[5] = _233; - _234[4] = _233; - _234[3] = _233; - _234[2] = _233; - _234[1] = _233; - _234[0] = _233; + zz_135[18] = zz_134; + zz_135[17] = zz_134; + zz_135[16] = zz_134; + zz_135[15] = zz_134; + zz_135[14] = zz_134; + zz_135[13] = zz_134; + zz_135[12] = zz_134; + zz_135[11] = zz_134; + zz_135[10] = zz_134; + zz_135[9] = zz_134; + zz_135[8] = zz_134; + zz_135[7] = zz_134; + zz_135[6] = zz_134; + zz_135[5] = zz_134; + zz_135[4] = zz_134; + zz_135[3] = zz_134; + zz_135[2] = zz_134; + zz_135[1] = zz_134; + zz_135[0] = zz_134; end - always @ (execute_INSTRUCTION or execute_BRANCH_CTRL or _227 or _228 or _231 or _234 or _235) + always @ (execute_BRANCH_CTRL or zz_131 or execute_INSTRUCTION or zz_133 or zz_135) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_binary_sequancial_JAL : begin - _236 = {{_227,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},_228}; + zz_136 = {{zz_131,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; end `BranchCtrlEnum_binary_sequancial_JALR : begin - _236 = {_231,execute_INSTRUCTION[31 : 20]}; + zz_136 = {zz_133,execute_INSTRUCTION[31 : 20]}; end default : begin - _236 = {{_234,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},_235}; + zz_136 = {{zz_135,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; end endcase end - always @ (writeBack_arbitration_isFiring or _48 or _49 or writeBack_FomalPlugin_haltFired or _54) - begin - _286 = writeBack_arbitration_isFiring; - if(_48)begin - _286 = _49; - end - if(writeBack_FomalPlugin_haltFired)begin - _286 = _54; - end - end - - always @ (_13 or _48 or _51) - begin - _287 = _13; - if(_48)begin - _287 = _51; - end - end - + assign execute_BranchPlugin_branch_src2 = zz_136; + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign zz_15 = {execute_BranchPlugin_branchAdder[31 : 1],((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequancial_JALR) ? 1'b0 : execute_BranchPlugin_branchAdder[0])}; + assign zz_81 = (memory_arbitration_isFiring && memory_BRANCH_DO); + assign zz_82 = memory_BRANCH_CALC; + assign zz_14 = decode_ALU_CTRL; + assign zz_12 = zz_47; + assign zz_32 = zz_140; + assign zz_27 = zz_51; + assign zz_30 = zz_38; + assign zz_11 = decode_SHIFT_CTRL; + assign zz_8 = execute_SHIFT_CTRL; + assign zz_9 = zz_46; + assign zz_21 = zz_185; + assign zz_19 = zz_186; + assign zz_6 = decode_ALU_BITWISE_CTRL; + assign zz_4 = zz_50; + assign zz_34 = zz_195; + assign zz_3 = decode_BRANCH_CTRL; + assign zz_1 = zz_49; + assign zz_16 = zz_198; + assign prefetch_arbitration_isFlushed = (((((prefetch_arbitration_flushAll || fetch_arbitration_flushAll) || decode_arbitration_flushAll) || execute_arbitration_flushAll) || memory_arbitration_flushAll) || writeBack_arbitration_flushAll); + assign fetch_arbitration_isFlushed = ((((fetch_arbitration_flushAll || decode_arbitration_flushAll) || execute_arbitration_flushAll) || memory_arbitration_flushAll) || writeBack_arbitration_flushAll); + assign decode_arbitration_isFlushed = (((decode_arbitration_flushAll || execute_arbitration_flushAll) || memory_arbitration_flushAll) || writeBack_arbitration_flushAll); + assign execute_arbitration_isFlushed = ((execute_arbitration_flushAll || memory_arbitration_flushAll) || writeBack_arbitration_flushAll); + assign memory_arbitration_isFlushed = (memory_arbitration_flushAll || writeBack_arbitration_flushAll); + assign writeBack_arbitration_isFlushed = writeBack_arbitration_flushAll; + assign prefetch_arbitration_isStuckByOthers = (prefetch_arbitration_haltByOther || (((((1'b0 || fetch_arbitration_haltItself) || decode_arbitration_haltItself) || execute_arbitration_haltItself) || memory_arbitration_haltItself) || writeBack_arbitration_haltItself)); + assign prefetch_arbitration_isStuck = (prefetch_arbitration_haltItself || prefetch_arbitration_isStuckByOthers); + assign prefetch_arbitration_isFiring = ((prefetch_arbitration_isValid && (! prefetch_arbitration_isStuck)) && (! prefetch_arbitration_removeIt)); + assign fetch_arbitration_isStuckByOthers = (fetch_arbitration_haltByOther || ((((1'b0 || decode_arbitration_haltItself) || execute_arbitration_haltItself) || memory_arbitration_haltItself) || writeBack_arbitration_haltItself)); + assign fetch_arbitration_isStuck = (fetch_arbitration_haltItself || fetch_arbitration_isStuckByOthers); + assign fetch_arbitration_isFiring = ((fetch_arbitration_isValid && (! fetch_arbitration_isStuck)) && (! fetch_arbitration_removeIt)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_haltItself) || memory_arbitration_haltItself) || writeBack_arbitration_haltItself)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_haltItself) || writeBack_arbitration_haltItself)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_haltItself)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (posedge clk) begin if(reset) begin - prefetch_arbitration_isValid <= _1; - fetch_arbitration_isValid <= _2; - decode_arbitration_isValid <= _3; - execute_arbitration_isValid <= _4; - memory_arbitration_isValid <= _5; - writeBack_arbitration_isValid <= _6; + prefetch_arbitration_isValid <= 1'b0; + fetch_arbitration_isValid <= 1'b0; + decode_arbitration_isValid <= 1'b0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; writeBack_FomalPlugin_order <= (64'b0000000000000000000000000000000000000000000000000000000000000000); - _44 <= _43; - _45 <= _43; - _46 <= _43; - _47 <= _43; - _48 <= _43; - writeBack_FomalPlugin_haltFired <= _52; + zz_84 <= zz_83; + zz_85 <= zz_83; + zz_86 <= zz_83; + zz_87 <= zz_83; + zz_88 <= zz_83; + writeBack_FomalPlugin_haltFired <= 1'b0; prefetch_PcManagerSimplePlugin_pcReg <= (32'b00000000000000000000000000000000); - prefetch_PcManagerSimplePlugin_inc <= _63; - prefetch_IBusSimplePlugin_pendingCmd <= _73; - _80 <= _79; - _138 <= _139; - _184 <= _186; - writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000); - writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000); + prefetch_PcManagerSimplePlugin_inc <= 1'b0; + prefetch_IBusSimplePlugin_pendingCmd <= 1'b0; + zz_89 <= 1'b0; + zz_113 <= 1'b1; + zz_125 <= 1'b0; + zz_197 <= (32'b00000000000000000000000000000000); + zz_163 <= (32'b00000000000000000000000000000000); end else begin - prefetch_arbitration_isValid <= _62; + if(writeBack_arbitration_isFiring)begin + writeBack_FomalPlugin_order <= (writeBack_FomalPlugin_order + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + end + zz_84 <= writeBack_FomalPlugin_haltRequest; + zz_85 <= zz_84; + zz_86 <= zz_85; + zz_87 <= zz_86; + zz_88 <= zz_87; + if((zz_204 && zz_205))begin + writeBack_FomalPlugin_haltFired <= 1'b1; + end + prefetch_arbitration_isValid <= 1'b1; + if(prefetch_PcManagerSimplePlugin_jump_pcLoad_valid)begin + prefetch_PcManagerSimplePlugin_inc <= 1'b0; + end + if(prefetch_arbitration_isFiring)begin + prefetch_PcManagerSimplePlugin_inc <= 1'b1; + end + if(prefetch_PcManagerSimplePlugin_samplePcNext)begin + prefetch_PcManagerSimplePlugin_pcReg <= prefetch_PcManagerSimplePlugin_pc; + end + if(iBus_rsp_ready)begin + prefetch_IBusSimplePlugin_pendingCmd <= 1'b0; + end + if((zz_206 && iBus_cmd_ready))begin + prefetch_IBusSimplePlugin_pendingCmd <= 1'b1; + end + if(iBus_rsp_ready)begin + zz_89 <= 1'b1; + end + if((! fetch_arbitration_isStuck))begin + zz_89 <= 1'b0; + end + zz_113 <= 1'b0; + zz_125 <= (zz_77 && writeBack_arbitration_isFiring); + if((! writeBack_arbitration_isStuck))begin + zz_163 <= memory_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + zz_197 <= zz_18; + end if(((! fetch_arbitration_isStuck) || fetch_arbitration_removeIt))begin - fetch_arbitration_isValid <= _279; + fetch_arbitration_isValid <= 1'b0; end if(((! prefetch_arbitration_isStuck) && (! prefetch_arbitration_removeIt)))begin fetch_arbitration_isValid <= prefetch_arbitration_isValid; end if(((! decode_arbitration_isStuck) || decode_arbitration_removeIt))begin - decode_arbitration_isValid <= _280; + decode_arbitration_isValid <= 1'b0; end if(((! fetch_arbitration_isStuck) && (! fetch_arbitration_removeIt)))begin decode_arbitration_isValid <= fetch_arbitration_isValid; end if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin - execute_arbitration_isValid <= _281; + execute_arbitration_isValid <= 1'b0; end if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin execute_arbitration_isValid <= decode_arbitration_isValid; end if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin - memory_arbitration_isValid <= _282; + memory_arbitration_isValid <= 1'b0; end if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin memory_arbitration_isValid <= execute_arbitration_isValid; end if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin - writeBack_arbitration_isValid <= _283; + writeBack_arbitration_isValid <= 1'b0; end if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - if(writeBack_arbitration_isFiring)begin - writeBack_FomalPlugin_order <= _10; - end - _44 <= writeBack_FomalPlugin_haltRequest; - _45 <= _44; - _46 <= _45; - _47 <= _46; - _48 <= _47; - if((_286 && _287))begin - writeBack_FomalPlugin_haltFired <= _53; - end - if(prefetch_PcManagerSimplePlugin_samplePcNext)begin - prefetch_PcManagerSimplePlugin_pcReg <= prefetch_PcManagerSimplePlugin_pc; - end - if(prefetch_PcManagerSimplePlugin_jump_pcLoad_valid)begin - prefetch_PcManagerSimplePlugin_inc <= _66; - end - if(prefetch_arbitration_isFiring)begin - prefetch_PcManagerSimplePlugin_inc <= _69; - end - if(iBus_rsp_ready)begin - prefetch_IBusSimplePlugin_pendingCmd <= _74; - end - if((_284 && iBus_cmd_ready))begin - prefetch_IBusSimplePlugin_pendingCmd <= _75; - end - if(iBus_rsp_ready)begin - _80 <= _81; - end - if((! fetch_arbitration_isStuck))begin - _80 <= _82; - end - _138 <= _137; - _184 <= (_21 && writeBack_arbitration_isFiring); - if((! writeBack_arbitration_isStuck))begin - writeBack_REGFILE_WRITE_DATA <= _178; - end - if((! writeBack_arbitration_isStuck))begin - writeBack_INSTRUCTION <= memory_INSTRUCTION; - end end end always @ (posedge clk) begin - if (!((! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck)) || (! _102))) begin - $display("ERROR DBusSimplePlugin doesn't allow memory stage stall when read happend"); + if((! zz_89))begin + zz_90 <= iBus_rsp_inst; end - if (!((! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_INSTRUCTION[5])) && writeBack_arbitration_isStuck)) || (! _110))) begin + if (!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin $display("ERROR DBusSimplePlugin doesn't allow memory stage stall when read happend"); end - RegFilePlugin_regFile_port0_data <= RegFilePlugin_regFile[RegFilePlugin_regFile_port0_address]; - RegFilePlugin_regFile_port1_data <= RegFilePlugin_regFile[RegFilePlugin_regFile_port1_address]; - if(RegFilePlugin_regFile_port2_enable)begin - RegFilePlugin_regFile[RegFilePlugin_regFile_port2_address] <= RegFilePlugin_regFile_port2_data; + if (!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_INSTRUCTION[5])) && writeBack_arbitration_isStuck))) begin + $display("ERROR DBusSimplePlugin doesn't allow memory stage stall when read happend"); end - if (!((prefetch_arbitration_removeIt == _261) || (! _262))) begin - $display("ERROR removeIt should never be asserted on this stage"); + zz_126 <= zz_80[11 : 7]; + if((! execute_arbitration_isStuck))begin + zz_137 <= decode_SRC_USE_SUB_LESS; end - if((! _80))begin - _83 <= iBus_rsp_inst; + if((! execute_arbitration_isStuck))begin + zz_138 <= decode_SRC2; end - _185 <= _11[11 : 7]; if((! memory_arbitration_isStuck))begin - memory_REGFILE_WRITE_DATA <= execute_REGFILE_WRITE_DATA; + zz_139 <= execute_BRANCH_CALC; end if((! execute_arbitration_isStuck))begin - execute_RS2_USE <= decode_RS2_USE; + zz_140 <= zz_13; + end + if((! execute_arbitration_isStuck))begin + zz_141 <= decode_BYPASSABLE_MEMORY_STAGE; end if((! memory_arbitration_isStuck))begin - memory_RS2_USE <= execute_RS2_USE; + zz_142 <= execute_BYPASSABLE_MEMORY_STAGE; end - if((! writeBack_arbitration_isStuck))begin - writeBack_RS2_USE <= memory_RS2_USE; + if((! fetch_arbitration_isStuck))begin + zz_143 <= zz_75; + end + if((! decode_arbitration_isStuck))begin + zz_144 <= zz_74; end if((! execute_arbitration_isStuck))begin - execute_RS1 <= _148; + zz_145 <= zz_73; end if((! memory_arbitration_isStuck))begin - memory_RS1 <= execute_RS1; + zz_146 <= zz_72; end if((! writeBack_arbitration_isStuck))begin - writeBack_RS1 <= memory_RS1; + zz_147 <= zz_71; end if((! execute_arbitration_isStuck))begin - execute_RS2 <= _153; - end - if((! memory_arbitration_isStuck))begin - memory_RS2 <= execute_RS2; + zz_148 <= decode_SRC_LESS_UNSIGNED; end - if((! writeBack_arbitration_isStuck))begin - writeBack_RS2 <= memory_RS2; + if((! execute_arbitration_isStuck))begin + zz_149 <= decode_REGFILE_WRITE_VALID; end if((! memory_arbitration_isStuck))begin - memory_FORMAL_MEM_WDATA <= execute_FORMAL_MEM_WDATA; + zz_150 <= execute_REGFILE_WRITE_VALID; end if((! writeBack_arbitration_isStuck))begin - writeBack_FORMAL_MEM_WDATA <= memory_FORMAL_MEM_WDATA; + zz_151 <= memory_REGFILE_WRITE_VALID; end if((! memory_arbitration_isStuck))begin - _246 <= execute_BRANCH_CALC; - end - if((! fetch_arbitration_isStuck))begin - _247 <= _76; + zz_152 <= execute_FORMAL_MEM_WMASK; end - if((! decode_arbitration_isStuck))begin - _248 <= fetch_PC; + if((! writeBack_arbitration_isStuck))begin + zz_153 <= memory_FORMAL_MEM_WMASK; end if((! execute_arbitration_isStuck))begin - _249 <= _160; + zz_154 <= zz_26; end if((! memory_arbitration_isStuck))begin - _250 <= execute_PC; + zz_155 <= execute_RS2; end if((! writeBack_arbitration_isStuck))begin - _251 <= memory_PC; + zz_156 <= memory_RS2; end - if((! memory_arbitration_isStuck))begin - memory_BRANCH_DO <= execute_BRANCH_DO; + if((! execute_arbitration_isStuck))begin + zz_157 <= decode_RS1_USE; end if((! memory_arbitration_isStuck))begin - _252 <= execute_MEMORY_ADDRESS_LOW; + zz_158 <= execute_RS1_USE; end if((! writeBack_arbitration_isStuck))begin - _253 <= memory_MEMORY_ADDRESS_LOW; - end - if((! execute_arbitration_isStuck))begin - execute_SRC2 <= decode_SRC2; + zz_159 <= memory_RS1_USE; end - if((! execute_arbitration_isStuck))begin - execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + if((! decode_arbitration_isStuck))begin + zz_160 <= zz_62; end if((! execute_arbitration_isStuck))begin - execute_RS1_USE <= decode_RS1_USE; + zz_161 <= decode_INSTRUCTION; end if((! memory_arbitration_isStuck))begin - memory_RS1_USE <= execute_RS1_USE; + zz_162 <= execute_INSTRUCTION; end - if((! writeBack_arbitration_isStuck))begin - writeBack_RS1_USE <= memory_RS1_USE; + if((! execute_arbitration_isStuck))begin + zz_164 <= decode_MEMORY_ENABLE; end if((! memory_arbitration_isStuck))begin - memory_FORMAL_MEM_RMASK <= execute_FORMAL_MEM_RMASK; + zz_165 <= execute_MEMORY_ENABLE; end if((! writeBack_arbitration_isStuck))begin - writeBack_FORMAL_MEM_RMASK <= memory_FORMAL_MEM_RMASK; + zz_166 <= memory_MEMORY_ENABLE; end if((! memory_arbitration_isStuck))begin - _254 <= execute_FORMAL_MEM_ADDR; + zz_167 <= execute_FORMAL_MEM_WDATA; end if((! writeBack_arbitration_isStuck))begin - _255 <= memory_FORMAL_MEM_ADDR; + zz_168 <= memory_FORMAL_MEM_WDATA; end - if((! fetch_arbitration_isStuck))begin - fetch_FORMAL_HALT <= _25; + if((! writeBack_arbitration_isStuck))begin + zz_169 <= memory_MEMORY_READ_DATA; end - if((! decode_arbitration_isStuck))begin - decode_FORMAL_HALT <= _29; + if((! execute_arbitration_isStuck))begin + zz_170 <= decode_BYPASSABLE_EXECUTE_STAGE; end if((! execute_arbitration_isStuck))begin - execute_FORMAL_HALT <= _32; + zz_171 <= zz_29; end if((! memory_arbitration_isStuck))begin - memory_FORMAL_HALT <= _35; + zz_172 <= execute_RS1; end if((! writeBack_arbitration_isStuck))begin - writeBack_FORMAL_HALT <= _38; + zz_173 <= memory_RS1; end if((! execute_arbitration_isStuck))begin - execute_BRANCH_CTRL <= decode_BRANCH_CTRL; + zz_174 <= decode_RS2_USE; end - if((! execute_arbitration_isStuck))begin - execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + if((! memory_arbitration_isStuck))begin + zz_175 <= execute_RS2_USE; end - if((! execute_arbitration_isStuck))begin - execute_ALU_BITWISE_CTRL <= decode_ALU_BITWISE_CTRL; + if((! writeBack_arbitration_isStuck))begin + zz_176 <= memory_RS2_USE; end if((! memory_arbitration_isStuck))begin - memory_FORMAL_MEM_WMASK <= execute_FORMAL_MEM_WMASK; + zz_177 <= execute_FORMAL_MEM_RMASK; end if((! writeBack_arbitration_isStuck))begin - writeBack_FORMAL_MEM_WMASK <= memory_FORMAL_MEM_WMASK; - end - if((! decode_arbitration_isStuck))begin - decode_INSTRUCTION <= _87; + zz_178 <= memory_FORMAL_MEM_RMASK; end if((! execute_arbitration_isStuck))begin - execute_INSTRUCTION <= decode_INSTRUCTION; - end - if((! memory_arbitration_isStuck))begin - memory_INSTRUCTION <= execute_INSTRUCTION; + zz_179 <= decode_SRC1; end if((! fetch_arbitration_isStuck))begin - _256 <= prefetch_FORMAL_PC_NEXT; + zz_180 <= prefetch_FORMAL_PC_NEXT; end if((! decode_arbitration_isStuck))begin - _257 <= fetch_FORMAL_PC_NEXT; + zz_181 <= fetch_FORMAL_PC_NEXT; end if((! execute_arbitration_isStuck))begin - _258 <= decode_FORMAL_PC_NEXT; + zz_182 <= decode_FORMAL_PC_NEXT; end if((! memory_arbitration_isStuck))begin - _259 <= execute_FORMAL_PC_NEXT; + zz_183 <= execute_FORMAL_PC_NEXT; end if((! writeBack_arbitration_isStuck))begin - _260 <= _72; + zz_184 <= zz_66; end if((! execute_arbitration_isStuck))begin - execute_ALU_CTRL <= decode_ALU_CTRL; - end - if((! writeBack_arbitration_isStuck))begin - writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; + zz_185 <= zz_10; end if((! memory_arbitration_isStuck))begin - memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; - end - if((! execute_arbitration_isStuck))begin - execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + zz_186 <= zz_7; end if((! memory_arbitration_isStuck))begin - memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; - end - if((! execute_arbitration_isStuck))begin - execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + zz_187 <= execute_SHIFT_RIGHT; end if((! memory_arbitration_isStuck))begin - memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + zz_188 <= execute_MEMORY_ADDRESS_LOW; end if((! writeBack_arbitration_isStuck))begin - writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + zz_189 <= memory_MEMORY_ADDRESS_LOW; + end + if((! fetch_arbitration_isStuck))begin + zz_190 <= zz_65; + end + if((! decode_arbitration_isStuck))begin + zz_191 <= fetch_PC; end if((! execute_arbitration_isStuck))begin - execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + zz_192 <= zz_25; end if((! memory_arbitration_isStuck))begin - memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + zz_193 <= execute_PC; end if((! writeBack_arbitration_isStuck))begin - writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + zz_194 <= memory_PC; end if((! execute_arbitration_isStuck))begin - execute_SRC1 <= decode_SRC1; + zz_195 <= zz_5; + end + if((! memory_arbitration_isStuck))begin + zz_196 <= execute_REGFILE_WRITE_DATA; end if((! execute_arbitration_isStuck))begin - execute_SHIFT_CTRL <= decode_SHIFT_CTRL; + zz_198 <= zz_2; end if((! memory_arbitration_isStuck))begin - memory_SHIFT_CTRL <= execute_SHIFT_CTRL; + zz_199 <= execute_BRANCH_DO; end - if((! execute_arbitration_isStuck))begin - execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + if((! memory_arbitration_isStuck))begin + zz_200 <= execute_FORMAL_MEM_ADDR; + end + if((! writeBack_arbitration_isStuck))begin + zz_201 <= memory_FORMAL_MEM_ADDR; + end + if (!(prefetch_arbitration_removeIt == 1'b0)) begin + $display("ERROR removeIt should never be asserted on this stage"); end end endmodule + diff --git a/cores/VexRiscv/imemcheck.sby b/cores/VexRiscv/imemcheck.sby new file mode 100644 index 0000000..2b6f0cc --- /dev/null +++ b/cores/VexRiscv/imemcheck.sby @@ -0,0 +1,21 @@ +[options] +mode bmc +append 0 +tbtop testbench.uut +depth 22 + +[engines] +smtbmc --presat --unroll boolector + +[script] +read_verilog -sv imemcheck.sv +read_verilog /home/spinalvm/hdl/formal/riscv-formal/cores/VexRiscv/VexRiscv.v +prep -nordff -top testbench + +[files] +imemcheck.sv +/home/spinalvm/hdl/formal/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh +/home/spinalvm/hdl/formal/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv +/home/spinalvm/hdl/formal/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv +/home/spinalvm/hdl/formal/riscv-formal/cores/picorv32/../../checks/rvfi_imem_check.sv + diff --git a/cores/VexRiscv/imemcheck.sv b/cores/VexRiscv/imemcheck.sv new file mode 100644 index 0000000..7c1106b --- /dev/null +++ b/cores/VexRiscv/imemcheck.sv @@ -0,0 +1,105 @@ +`define RISCV_FORMAL +`define RISCV_FORMAL_NRET 1 +`define RISCV_FORMAL_XLEN 32 +`define RISCV_FORMAL_ILEN 32 +`include "rvfi_macros.vh" +`include "rvfi_channel.sv" +`include "rvfi_imem_check.sv" + +module testbench ( + input clk +); + reg reset = 1; + + always @(posedge clk) + reset <= 0; + + + + + (* keep *) wire iBus_cmd_valid; + (* keep *) wire [31:0] iBus_cmd_payload_pc; + (* keep *) `rvformal_rand_reg iBus_cmd_ready; + (* keep *) `rvformal_rand_reg iBus_rsp_ready; + (* keep *) `rvformal_rand_reg [31:0] iBus_rsp_inst; + + + (* keep *) wire dBus_cmd_valid; + (* keep *) wire dBus_cmd_payload_wr; + (* keep *) wire [31:0] dBus_cmd_payload_address; + (* keep *) wire [31:0] dBus_cmd_payload_data; + (* keep *) wire [1:0] dBus_cmd_payload_size; + (* keep *) `rvformal_rand_reg dBus_cmd_ready; + (* keep *) `rvformal_rand_reg dBus_rsp_ready; + (* keep *) `rvformal_rand_reg [31:0] dBus_rsp_data; + + + + `RVFI_WIRES + + (* keep *) wire [31:0] imem_addr; + (* keep *) wire [15:0] imem_data; + + rvfi_imem_check checker_inst ( + .clock (clk ), + .reset (reset ), + .enable (1'b1 ), + .imem_addr (imem_addr), + .imem_data (imem_data), + `RVFI_CONN + ); + + (* keep *) wire imem_last_valid; + (* keep *) wire [31:0] imem_last_addr; + + always @(posedge clk) begin + if (reset) begin + imem_last_valid <= 0; + end else begin + if(imem_last_valid) begin + if (imem_last_addr == imem_addr) + assume(iBus_rsp_inst[15:0] == imem_data); + if (imem_last_addr+2 == imem_addr) + assume(iBus_rsp_inst[31:16] == imem_data); + end + if(iBus_rsp_ready) begin + imem_last_valid <= 0; + end + if(iBus_cmd_valid && iBus_cmd_ready) begin + imem_last_valid <= 1; + imem_last_addr <= iBus_cmd_payload_pc; + end + end + + end + + + + + + VexRiscv uut ( + .clk (clk ), + .reset (reset ), + + .iBus_cmd_valid (iBus_cmd_valid), + .iBus_cmd_ready (iBus_cmd_ready), + .iBus_cmd_payload_pc (iBus_cmd_payload_pc ), + .iBus_rsp_ready(iBus_rsp_ready), + .iBus_rsp_inst (iBus_rsp_inst), + .iBus_rsp_error(1'b0), + + .dBus_cmd_valid(dBus_cmd_valid), + .dBus_cmd_payload_wr(dBus_cmd_payload_wr), + .dBus_cmd_payload_address(dBus_cmd_payload_address), + .dBus_cmd_payload_data(dBus_cmd_payload_data), + .dBus_cmd_payload_size(dBus_cmd_payload_size), + .dBus_cmd_ready(dBus_cmd_ready), + .dBus_rsp_ready(dBus_rsp_ready), + .dBus_rsp_data(dBus_rsp_data), + .dBus_rsp_error(1'b0), + + `RVFI_CONN + ); + +endmodule + From 1be1a23cd5c2941872f0017cfbcf31fb0e2620e3 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sun, 26 Nov 2017 15:36:13 +0100 Subject: [PATCH 2/4] Add dmemcheck --- cores/VexRiscv/README.md | 7 +- cores/VexRiscv/VexRiscv.v | 1321 +++++++++++++++++----------------- cores/VexRiscv/checks.cfg | 4 +- cores/VexRiscv/dmemcheck.sby | 21 + cores/VexRiscv/dmemcheck.sv | 116 +++ 5 files changed, 812 insertions(+), 657 deletions(-) create mode 100644 cores/VexRiscv/dmemcheck.sby create mode 100644 cores/VexRiscv/dmemcheck.sv diff --git a/cores/VexRiscv/README.md b/cores/VexRiscv/README.md index 6e6341e..70184ca 100644 --- a/cores/VexRiscv/README.md +++ b/cores/VexRiscv/README.md @@ -3,7 +3,7 @@ riscv-formal proofs for VexRiscv ================================ ### Current state: -Test a simple VexRiscv configuration (https://github.com/SpinalHDL/VexRiscv/blob/formal/src/main/scala/vexriscv/demo/FormalSimple.scala) +Test a simple VexRiscv configuration (https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/scala/vexriscv/demo/FormalSimple.scala) All standards checks are passing - Instruction Checks @@ -14,6 +14,7 @@ All standards checks are passing Other tests passing : - Instruction Memory check +- Data Memory check ### Quickstart guide: @@ -38,15 +39,15 @@ export test=insn_beq_ch0; rm -r checks/$test; make -C checks -j$(nproc) $test/PA ``` -Running the instruction memory check : +Running the memory checks : ``` sby -f imemcheck.sby +sby -f dmemcheck.sby ``` ### Todo: - Integrate others VexRiscv configurations into the framework -- Add Data Memcheck check - Add Checking for equivalence of core with and without RVFI check - Add Complete check - Add Cover check diff --git a/cores/VexRiscv/VexRiscv.v b/cores/VexRiscv/VexRiscv.v index 8329845..29a6413 100644 --- a/cores/VexRiscv/VexRiscv.v +++ b/cores/VexRiscv/VexRiscv.v @@ -1,5 +1,5 @@ // Generator : SpinalHDL v0.11.3 git head : 4d8502333f4f7d6be245912fd85227ba7847abbd -// Date : 24/11/2017, 12:08:46 +// Date : 26/11/2017, 14:03:00 // Component : VexRiscv @@ -9,33 +9,33 @@ `define BranchCtrlEnum_binary_sequancial_JAL 2'b10 `define BranchCtrlEnum_binary_sequancial_JALR 2'b11 -`define Src2CtrlEnum_binary_sequancial_type [1:0] -`define Src2CtrlEnum_binary_sequancial_RS 2'b00 -`define Src2CtrlEnum_binary_sequancial_IMI 2'b01 -`define Src2CtrlEnum_binary_sequancial_IMS 2'b10 -`define Src2CtrlEnum_binary_sequancial_PC 2'b11 - -`define AluCtrlEnum_binary_sequancial_type [1:0] -`define AluCtrlEnum_binary_sequancial_ADD_SUB 2'b00 -`define AluCtrlEnum_binary_sequancial_SLT_SLTU 2'b01 -`define AluCtrlEnum_binary_sequancial_BITWISE 2'b10 - `define AluBitwiseCtrlEnum_binary_sequancial_type [1:0] `define AluBitwiseCtrlEnum_binary_sequancial_XOR_1 2'b00 `define AluBitwiseCtrlEnum_binary_sequancial_OR_1 2'b01 `define AluBitwiseCtrlEnum_binary_sequancial_AND_1 2'b10 `define AluBitwiseCtrlEnum_binary_sequancial_SRC1 2'b11 +`define Src1CtrlEnum_binary_sequancial_type [1:0] +`define Src1CtrlEnum_binary_sequancial_RS 2'b00 +`define Src1CtrlEnum_binary_sequancial_IMU 2'b01 +`define Src1CtrlEnum_binary_sequancial_FOUR 2'b10 + +`define Src2CtrlEnum_binary_sequancial_type [1:0] +`define Src2CtrlEnum_binary_sequancial_RS 2'b00 +`define Src2CtrlEnum_binary_sequancial_IMI 2'b01 +`define Src2CtrlEnum_binary_sequancial_IMS 2'b10 +`define Src2CtrlEnum_binary_sequancial_PC 2'b11 + `define ShiftCtrlEnum_binary_sequancial_type [1:0] `define ShiftCtrlEnum_binary_sequancial_DISABLE_1 2'b00 `define ShiftCtrlEnum_binary_sequancial_SLL_1 2'b01 `define ShiftCtrlEnum_binary_sequancial_SRL_1 2'b10 `define ShiftCtrlEnum_binary_sequancial_SRA_1 2'b11 -`define Src1CtrlEnum_binary_sequancial_type [1:0] -`define Src1CtrlEnum_binary_sequancial_RS 2'b00 -`define Src1CtrlEnum_binary_sequancial_IMU 2'b01 -`define Src1CtrlEnum_binary_sequancial_FOUR 2'b10 +`define AluCtrlEnum_binary_sequancial_type [1:0] +`define AluCtrlEnum_binary_sequancial_ADD_SUB 2'b00 +`define AluCtrlEnum_binary_sequancial_SLT_SLTU 2'b01 +`define AluCtrlEnum_binary_sequancial_BITWISE 2'b10 module VexRiscv ( output rvfi_valid, @@ -74,42 +74,42 @@ module VexRiscv ( input [31:0] dBus_rsp_data, input clk, input reset); - reg [31:0] zz_202; - reg [31:0] zz_203; - reg zz_204; - reg zz_205; - wire zz_206; - wire [1:0] zz_207; - wire [31:0] zz_208; + reg [31:0] zz_205; + reg [31:0] zz_206; + reg zz_207; + reg zz_208; wire zz_209; - wire zz_210; + wire [1:0] zz_210; wire [31:0] zz_211; - wire [1:0] zz_212; - wire [31:0] zz_213; - wire [0:0] zz_214; - wire [0:0] zz_215; - wire [0:0] zz_216; + wire zz_212; + wire zz_213; + wire [31:0] zz_214; + wire [1:0] zz_215; + wire [31:0] zz_216; wire [0:0] zz_217; wire [0:0] zz_218; wire [0:0] zz_219; wire [0:0] zz_220; wire [0:0] zz_221; - wire [11:0] zz_222; - wire [11:0] zz_223; - wire [31:0] zz_224; - wire [31:0] zz_225; - wire [31:0] zz_226; + wire [0:0] zz_222; + wire [0:0] zz_223; + wire [0:0] zz_224; + wire [11:0] zz_225; + wire [11:0] zz_226; wire [31:0] zz_227; wire [31:0] zz_228; - wire [1:0] zz_229; - wire [1:0] zz_230; - wire [1:0] zz_231; - wire [32:0] zz_232; - wire [31:0] zz_233; - wire [32:0] zz_234; - wire [19:0] zz_235; - wire [11:0] zz_236; - wire [11:0] zz_237; + wire [31:0] zz_229; + wire [31:0] zz_230; + wire [31:0] zz_231; + wire [1:0] zz_232; + wire [1:0] zz_233; + wire [1:0] zz_234; + wire [32:0] zz_235; + wire [31:0] zz_236; + wire [32:0] zz_237; + wire [19:0] zz_238; + wire [11:0] zz_239; + wire [11:0] zz_240; wire [31:0] writeBack_FORMAL_MEM_ADDR; wire [31:0] memory_FORMAL_MEM_ADDR; wire [31:0] execute_FORMAL_MEM_ADDR; @@ -119,16 +119,14 @@ module VexRiscv ( wire `BranchCtrlEnum_binary_sequancial_type zz_2; wire `BranchCtrlEnum_binary_sequancial_type zz_3; wire [31:0] writeBack_REGFILE_WRITE_DATA; - wire [31:0] memory_REGFILE_WRITE_DATA; wire [31:0] execute_REGFILE_WRITE_DATA; - wire `AluBitwiseCtrlEnum_binary_sequancial_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_binary_sequancial_type zz_4; - wire `AluBitwiseCtrlEnum_binary_sequancial_type zz_5; - wire `AluBitwiseCtrlEnum_binary_sequancial_type zz_6; + wire decode_SRC_LESS_UNSIGNED; + wire `AluCtrlEnum_binary_sequancial_type decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequancial_type zz_4; + wire `AluCtrlEnum_binary_sequancial_type zz_5; + wire `AluCtrlEnum_binary_sequancial_type zz_6; wire [31:0] memory_PC; wire [31:0] fetch_PC; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; wire [31:0] execute_SHIFT_RIGHT; wire `ShiftCtrlEnum_binary_sequancial_type zz_7; wire `ShiftCtrlEnum_binary_sequancial_type zz_8; @@ -142,7 +140,7 @@ module VexRiscv ( wire [31:0] decode_FORMAL_PC_NEXT; wire [31:0] fetch_FORMAL_PC_NEXT; wire [31:0] prefetch_FORMAL_PC_NEXT; - wire [31:0] decode_SRC1; + wire [31:0] decode_SRC2; wire [3:0] writeBack_FORMAL_MEM_RMASK; wire [3:0] memory_FORMAL_MEM_RMASK; wire [3:0] execute_FORMAL_MEM_RMASK; @@ -152,7 +150,6 @@ module VexRiscv ( wire [31:0] writeBack_RS1; wire [31:0] memory_RS1; wire [31:0] decode_RS1; - wire decode_BYPASSABLE_EXECUTE_STAGE; wire [31:0] memory_MEMORY_READ_DATA; wire [31:0] writeBack_FORMAL_MEM_WDATA; wire [31:0] memory_FORMAL_MEM_WDATA; @@ -168,23 +165,25 @@ module VexRiscv ( wire [3:0] writeBack_FORMAL_MEM_WMASK; wire [3:0] memory_FORMAL_MEM_WMASK; wire [3:0] execute_FORMAL_MEM_WMASK; - wire decode_SRC_LESS_UNSIGNED; + wire decode_SRC_USE_SUB_LESS; wire writeBack_FORMAL_HALT; wire memory_FORMAL_HALT; wire execute_FORMAL_HALT; wire decode_FORMAL_HALT; wire fetch_FORMAL_HALT; wire prefetch_FORMAL_HALT; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; wire [31:0] writeBack_FORMAL_MEM_RDATA; + wire decode_BYPASSABLE_EXECUTE_STAGE; wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; - wire `AluCtrlEnum_binary_sequancial_type decode_ALU_CTRL; - wire `AluCtrlEnum_binary_sequancial_type zz_12; - wire `AluCtrlEnum_binary_sequancial_type zz_13; - wire `AluCtrlEnum_binary_sequancial_type zz_14; wire [31:0] execute_BRANCH_CALC; - wire [31:0] decode_SRC2; - wire decode_SRC_USE_SUB_LESS; + wire [31:0] decode_SRC1; + wire `AluBitwiseCtrlEnum_binary_sequancial_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequancial_type zz_12; + wire `AluBitwiseCtrlEnum_binary_sequancial_type zz_13; + wire `AluBitwiseCtrlEnum_binary_sequancial_type zz_14; wire [31:0] memory_BRANCH_CALC; wire memory_BRANCH_DO; wire [31:0] zz_15; @@ -239,23 +238,25 @@ module VexRiscv ( wire decode_INSTRUCTION_READY; wire `Src1CtrlEnum_binary_sequancial_type zz_38; wire zz_39; - wire zz_40; + wire `Src2CtrlEnum_binary_sequancial_type zz_40; wire zz_41; wire zz_42; wire zz_43; wire zz_44; wire zz_45; - wire `ShiftCtrlEnum_binary_sequancial_type zz_46; - wire `AluCtrlEnum_binary_sequancial_type zz_47; + wire `AluBitwiseCtrlEnum_binary_sequancial_type zz_46; + wire `ShiftCtrlEnum_binary_sequancial_type zz_47; wire zz_48; - wire `BranchCtrlEnum_binary_sequancial_type zz_49; - wire `AluBitwiseCtrlEnum_binary_sequancial_type zz_50; - wire `Src2CtrlEnum_binary_sequancial_type zz_51; + wire zz_49; + wire `BranchCtrlEnum_binary_sequancial_type zz_50; + wire `AluCtrlEnum_binary_sequancial_type zz_51; wire zz_52; wire [31:0] zz_53; wire writeBack_MEMORY_ENABLE; wire [1:0] writeBack_MEMORY_ADDRESS_LOW; wire [31:0] writeBack_MEMORY_READ_DATA; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_ALIGNEMENT_FAULT; wire [31:0] memory_INSTRUCTION; wire memory_MEMORY_ENABLE; wire [31:0] zz_54; @@ -350,19 +351,20 @@ module VexRiscv ( wire writeBack_arbitration_isStuckByOthers; wire writeBack_arbitration_isFlushed; wire writeBack_arbitration_isFiring/* verilator public */ ; + reg zz_81; wire decodeExceptionPort_valid; wire [3:0] decodeExceptionPort_payload_code; wire [31:0] decodeExceptionPort_payload_badAddr; - wire zz_81; - wire [31:0] zz_82; + wire zz_82; + wire [31:0] zz_83; reg [63:0] writeBack_FomalPlugin_order; reg writeBack_FomalPlugin_haltRequest; - wire zz_83; - reg zz_84; + wire zz_84; reg zz_85; reg zz_86; reg zz_87; reg zz_88; + reg zz_89; reg writeBack_FomalPlugin_haltFired; reg [31:0] prefetch_PcManagerSimplePlugin_pcReg/* verilator public */ ; reg prefetch_PcManagerSimplePlugin_inc; @@ -372,173 +374,175 @@ module VexRiscv ( wire prefetch_PcManagerSimplePlugin_jump_pcLoad_valid; wire [31:0] prefetch_PcManagerSimplePlugin_jump_pcLoad_payload; reg prefetch_IBusSimplePlugin_pendingCmd; - reg zz_89; - reg [31:0] zz_90; + reg zz_90; reg [31:0] zz_91; - reg [3:0] execute_DBusSimplePlugin_formalMask; + reg [31:0] zz_92; + reg [3:0] zz_93; + wire [3:0] execute_DBusSimplePlugin_formalMask; reg [31:0] writeBack_DBusSimplePlugin_rspShifted; - wire zz_92; - reg [31:0] zz_93; wire zz_94; reg [31:0] zz_95; + wire zz_96; + reg [31:0] zz_97; reg [31:0] writeBack_DBusSimplePlugin_rspFormated; - wire [19:0] zz_96; - wire zz_97; - wire zz_98; + wire [19:0] zz_98; wire zz_99; wire zz_100; wire zz_101; wire zz_102; wire zz_103; wire zz_104; - wire `Src2CtrlEnum_binary_sequancial_type zz_105; - wire `AluBitwiseCtrlEnum_binary_sequancial_type zz_106; - wire `BranchCtrlEnum_binary_sequancial_type zz_107; - wire `AluCtrlEnum_binary_sequancial_type zz_108; + wire zz_105; + wire zz_106; + wire `AluCtrlEnum_binary_sequancial_type zz_107; + wire `BranchCtrlEnum_binary_sequancial_type zz_108; wire `ShiftCtrlEnum_binary_sequancial_type zz_109; - wire `Src1CtrlEnum_binary_sequancial_type zz_110; + wire `AluBitwiseCtrlEnum_binary_sequancial_type zz_110; + wire `Src2CtrlEnum_binary_sequancial_type zz_111; + wire `Src1CtrlEnum_binary_sequancial_type zz_112; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; - wire zz_111; + wire zz_113; wire [31:0] decode_RegFilePlugin_rs2Data; - wire zz_112; + wire zz_114; reg writeBack_RegFilePlugin_regFileWrite_valid/* verilator public */ ; wire [4:0] writeBack_RegFilePlugin_regFileWrite_payload_address/* verilator public */ ; wire [31:0] writeBack_RegFilePlugin_regFileWrite_payload_data/* verilator public */ ; - reg zz_113; + reg zz_115; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] zz_114; - reg [31:0] zz_115; - wire zz_116; - reg [19:0] zz_117; + reg [31:0] zz_116; + reg [31:0] zz_117; wire zz_118; reg [19:0] zz_119; - reg [31:0] zz_120; + wire zz_120; + reg [19:0] zz_121; + reg [31:0] zz_122; wire [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrielShifterPlugin_amplitude; - reg [31:0] zz_121; + reg [31:0] zz_123; wire [31:0] execute_FullBarrielShifterPlugin_reversed; - reg [31:0] zz_122; - reg zz_123; - reg zz_124; + reg [31:0] zz_124; reg zz_125; - reg [4:0] zz_126; + reg zz_126; + reg zz_127; + reg [4:0] zz_128; wire execute_BranchPlugin_eq; - wire [2:0] zz_127; - reg zz_128; - reg zz_129; + wire [2:0] zz_129; + reg zz_130; + reg zz_131; wire [31:0] execute_BranchPlugin_branch_src1; - wire zz_130; - reg [10:0] zz_131; wire zz_132; - reg [19:0] zz_133; + reg [10:0] zz_133; wire zz_134; - reg [18:0] zz_135; - reg [31:0] zz_136; + reg [19:0] zz_135; + wire zz_136; + reg [18:0] zz_137; + reg [31:0] zz_138; wire [31:0] execute_BranchPlugin_branch_src2; wire [31:0] execute_BranchPlugin_branchAdder; - reg zz_137; - reg [31:0] zz_138; - reg [31:0] zz_139; - reg `AluCtrlEnum_binary_sequancial_type zz_140; - reg zz_141; + reg `AluBitwiseCtrlEnum_binary_sequancial_type zz_139; + reg [31:0] zz_140; + reg [31:0] zz_141; reg zz_142; reg zz_143; reg zz_144; - reg zz_145; - reg zz_146; + reg [1:0] zz_145; + reg [1:0] zz_146; reg zz_147; reg zz_148; reg zz_149; reg zz_150; reg zz_151; - reg [3:0] zz_152; - reg [3:0] zz_153; - reg [31:0] zz_154; - reg [31:0] zz_155; - reg [31:0] zz_156; - reg zz_157; - reg zz_158; - reg zz_159; + reg zz_152; + reg zz_153; + reg zz_154; + reg zz_155; + reg [3:0] zz_156; + reg [3:0] zz_157; + reg [31:0] zz_158; + reg [31:0] zz_159; reg [31:0] zz_160; - reg [31:0] zz_161; - reg [31:0] zz_162; - reg [31:0] zz_163; + reg zz_161; + reg zz_162; + reg zz_163; reg zz_164; - reg zz_165; - reg zz_166; + reg [31:0] zz_165; + reg [31:0] zz_166; reg [31:0] zz_167; reg [31:0] zz_168; - reg [31:0] zz_169; + reg zz_169; reg zz_170; - reg [31:0] zz_171; + reg zz_171; reg [31:0] zz_172; reg [31:0] zz_173; - reg zz_174; - reg zz_175; - reg zz_176; - reg [3:0] zz_177; - reg [3:0] zz_178; - reg [31:0] zz_179; - reg [31:0] zz_180; - reg [31:0] zz_181; - reg [31:0] zz_182; + reg [31:0] zz_174; + reg [31:0] zz_175; + reg [31:0] zz_176; + reg [31:0] zz_177; + reg zz_178; + reg zz_179; + reg zz_180; + reg [3:0] zz_181; + reg [3:0] zz_182; reg [31:0] zz_183; reg [31:0] zz_184; - reg `ShiftCtrlEnum_binary_sequancial_type zz_185; - reg `ShiftCtrlEnum_binary_sequancial_type zz_186; + reg [31:0] zz_185; + reg [31:0] zz_186; reg [31:0] zz_187; - reg [1:0] zz_188; - reg [1:0] zz_189; - reg [31:0] zz_190; + reg [31:0] zz_188; + reg `ShiftCtrlEnum_binary_sequancial_type zz_189; + reg `ShiftCtrlEnum_binary_sequancial_type zz_190; reg [31:0] zz_191; reg [31:0] zz_192; reg [31:0] zz_193; reg [31:0] zz_194; - reg `AluBitwiseCtrlEnum_binary_sequancial_type zz_195; + reg [31:0] zz_195; reg [31:0] zz_196; - reg [31:0] zz_197; - reg `BranchCtrlEnum_binary_sequancial_type zz_198; - reg zz_199; + reg `AluCtrlEnum_binary_sequancial_type zz_197; + reg zz_198; + reg [31:0] zz_199; reg [31:0] zz_200; - reg [31:0] zz_201; + reg `BranchCtrlEnum_binary_sequancial_type zz_201; + reg zz_202; + reg [31:0] zz_203; + reg [31:0] zz_204; reg [31:0] RegFilePlugin_regFile [0:31]/* verilator public */ ; - assign rvfi_valid = zz_204; - assign rvfi_halt = zz_205; - assign iBus_cmd_valid = zz_206; - assign dBus_cmd_payload_size = zz_207; - assign dBus_cmd_payload_address = zz_208; - assign dBus_cmd_valid = zz_209; - assign dBus_cmd_payload_wr = zz_210; - assign dBus_cmd_payload_data = zz_211; - assign zz_212 = writeBack_INSTRUCTION[13 : 12]; - assign zz_213 = {29'd0, {prefetch_PcManagerSimplePlugin_inc,(2'b00)}}; - assign zz_214 = zz_96[6 : 6]; - assign zz_215 = zz_96[11 : 11]; - assign zz_216 = zz_96[12 : 12]; - assign zz_217 = zz_96[13 : 13]; - assign zz_218 = zz_96[14 : 14]; - assign zz_219 = zz_96[15 : 15]; - assign zz_220 = zz_96[16 : 16]; - assign zz_221 = zz_96[17 : 17]; - assign zz_222 = decode_INSTRUCTION[31 : 20]; - assign zz_223 = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}; - assign zz_224 = ($signed(zz_225) + $signed(zz_228)); - assign zz_225 = ($signed(zz_226) + $signed(zz_227)); - assign zz_226 = execute_SRC1; - assign zz_227 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign zz_228 = {{30{zz_229[1]}}, zz_229}; - assign zz_229 = (execute_SRC_USE_SUB_LESS ? zz_230 : zz_231); - assign zz_230 = (2'b01); - assign zz_231 = (2'b00); - assign zz_232 = ($signed(zz_234) >>> execute_FullBarrielShifterPlugin_amplitude); - assign zz_233 = zz_232[31 : 0]; - assign zz_234 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequancial_SRA_1) && execute_FullBarrielShifterPlugin_reversed[31]),execute_FullBarrielShifterPlugin_reversed}; - assign zz_235 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign zz_236 = execute_INSTRUCTION[31 : 20]; - assign zz_237 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign rvfi_valid = zz_207; + assign rvfi_halt = zz_208; + assign iBus_cmd_valid = zz_209; + assign dBus_cmd_payload_size = zz_210; + assign dBus_cmd_payload_address = zz_211; + assign dBus_cmd_valid = zz_212; + assign dBus_cmd_payload_wr = zz_213; + assign dBus_cmd_payload_data = zz_214; + assign zz_215 = writeBack_INSTRUCTION[13 : 12]; + assign zz_216 = {29'd0, {prefetch_PcManagerSimplePlugin_inc,(2'b00)}}; + assign zz_217 = zz_98[4 : 4]; + assign zz_218 = zz_98[5 : 5]; + assign zz_219 = zz_98[10 : 10]; + assign zz_220 = zz_98[11 : 11]; + assign zz_221 = zz_98[12 : 12]; + assign zz_222 = zz_98[13 : 13]; + assign zz_223 = zz_98[14 : 14]; + assign zz_224 = zz_98[17 : 17]; + assign zz_225 = decode_INSTRUCTION[31 : 20]; + assign zz_226 = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}; + assign zz_227 = ($signed(zz_228) + $signed(zz_231)); + assign zz_228 = ($signed(zz_229) + $signed(zz_230)); + assign zz_229 = execute_SRC1; + assign zz_230 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign zz_231 = {{30{zz_232[1]}}, zz_232}; + assign zz_232 = (execute_SRC_USE_SUB_LESS ? zz_233 : zz_234); + assign zz_233 = (2'b01); + assign zz_234 = (2'b00); + assign zz_235 = ($signed(zz_237) >>> execute_FullBarrielShifterPlugin_amplitude); + assign zz_236 = zz_235[31 : 0]; + assign zz_237 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequancial_SRA_1) && execute_FullBarrielShifterPlugin_reversed[31]),execute_FullBarrielShifterPlugin_reversed}; + assign zz_238 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign zz_239 = execute_INSTRUCTION[31 : 20]; + assign zz_240 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; always @ (posedge clk) begin if(zz_35) begin @@ -548,103 +552,102 @@ module VexRiscv ( always @ (posedge clk) begin - if(zz_111) begin - zz_202 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(zz_113) begin + zz_205 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(zz_112) begin - zz_203 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(zz_114) begin + zz_206 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end - assign writeBack_FORMAL_MEM_ADDR = zz_201; - assign memory_FORMAL_MEM_ADDR = zz_200; + assign writeBack_FORMAL_MEM_ADDR = zz_204; + assign memory_FORMAL_MEM_ADDR = zz_203; assign execute_FORMAL_MEM_ADDR = zz_58; assign execute_BRANCH_DO = zz_17; assign decode_BRANCH_CTRL = zz_1; assign zz_2 = zz_3; - assign writeBack_REGFILE_WRITE_DATA = zz_197; - assign memory_REGFILE_WRITE_DATA = zz_196; + assign writeBack_REGFILE_WRITE_DATA = zz_200; assign execute_REGFILE_WRITE_DATA = zz_33; - assign decode_ALU_BITWISE_CTRL = zz_4; + assign decode_SRC_LESS_UNSIGNED = zz_43; + assign decode_ALU_CTRL = zz_4; assign zz_5 = zz_6; - assign memory_PC = zz_193; - assign fetch_PC = zz_190; - assign memory_MEMORY_ADDRESS_LOW = zz_188; - assign execute_MEMORY_ADDRESS_LOW = zz_59; + assign memory_PC = zz_195; + assign fetch_PC = zz_192; assign execute_SHIFT_RIGHT = zz_20; assign zz_7 = zz_8; assign decode_SHIFT_CTRL = zz_9; assign zz_10 = zz_11; - assign writeBack_FORMAL_PC_NEXT = zz_184; - assign memory_FORMAL_PC_NEXT = zz_183; - assign execute_FORMAL_PC_NEXT = zz_182; - assign decode_FORMAL_PC_NEXT = zz_181; - assign fetch_FORMAL_PC_NEXT = zz_180; + assign writeBack_FORMAL_PC_NEXT = zz_188; + assign memory_FORMAL_PC_NEXT = zz_187; + assign execute_FORMAL_PC_NEXT = zz_186; + assign decode_FORMAL_PC_NEXT = zz_185; + assign fetch_FORMAL_PC_NEXT = zz_184; assign prefetch_FORMAL_PC_NEXT = zz_67; - assign decode_SRC1 = zz_31; - assign writeBack_FORMAL_MEM_RMASK = zz_178; - assign memory_FORMAL_MEM_RMASK = zz_177; + assign decode_SRC2 = zz_28; + assign writeBack_FORMAL_MEM_RMASK = zz_182; + assign memory_FORMAL_MEM_RMASK = zz_181; assign execute_FORMAL_MEM_RMASK = zz_56; - assign writeBack_RS2_USE = zz_176; - assign memory_RS2_USE = zz_175; - assign execute_RS2_USE = zz_174; - assign writeBack_RS1 = zz_173; - assign memory_RS1 = zz_172; + assign writeBack_RS2_USE = zz_180; + assign memory_RS2_USE = zz_179; + assign execute_RS2_USE = zz_178; + assign writeBack_RS1 = zz_177; + assign memory_RS1 = zz_176; assign decode_RS1 = zz_37; - assign decode_BYPASSABLE_EXECUTE_STAGE = zz_44; assign memory_MEMORY_READ_DATA = zz_54; - assign writeBack_FORMAL_MEM_WDATA = zz_168; - assign memory_FORMAL_MEM_WDATA = zz_167; + assign writeBack_FORMAL_MEM_WDATA = zz_173; + assign memory_FORMAL_MEM_WDATA = zz_172; assign execute_FORMAL_MEM_WDATA = zz_55; - assign decode_MEMORY_ENABLE = zz_43; + assign decode_MEMORY_ENABLE = zz_45; assign fetch_INSTRUCTION = zz_64; - assign writeBack_RS1_USE = zz_159; - assign memory_RS1_USE = zz_158; - assign execute_RS1_USE = zz_157; - assign writeBack_RS2 = zz_156; - assign memory_RS2 = zz_155; + assign writeBack_RS1_USE = zz_164; + assign memory_RS1_USE = zz_163; + assign execute_RS1_USE = zz_162; + assign writeBack_RS2 = zz_160; + assign memory_RS2 = zz_159; assign decode_RS2 = zz_36; - assign writeBack_FORMAL_MEM_WMASK = zz_153; - assign memory_FORMAL_MEM_WMASK = zz_152; + assign writeBack_FORMAL_MEM_WMASK = zz_157; + assign memory_FORMAL_MEM_WMASK = zz_156; assign execute_FORMAL_MEM_WMASK = zz_57; - assign decode_SRC_LESS_UNSIGNED = zz_48; - assign writeBack_FORMAL_HALT = zz_147; - assign memory_FORMAL_HALT = zz_146; - assign execute_FORMAL_HALT = zz_145; - assign decode_FORMAL_HALT = zz_144; - assign fetch_FORMAL_HALT = zz_143; + assign decode_SRC_USE_SUB_LESS = zz_49; + assign writeBack_FORMAL_HALT = zz_151; + assign memory_FORMAL_HALT = zz_150; + assign execute_FORMAL_HALT = zz_149; + assign decode_FORMAL_HALT = zz_148; + assign fetch_FORMAL_HALT = zz_147; assign prefetch_FORMAL_HALT = zz_70; + assign memory_MEMORY_ADDRESS_LOW = zz_145; + assign execute_MEMORY_ADDRESS_LOW = zz_59; assign writeBack_FORMAL_MEM_RDATA = zz_53; - assign execute_BYPASSABLE_MEMORY_STAGE = zz_141; - assign decode_BYPASSABLE_MEMORY_STAGE = zz_40; - assign decode_ALU_CTRL = zz_12; - assign zz_13 = zz_14; + assign decode_BYPASSABLE_EXECUTE_STAGE = zz_41; + assign execute_BYPASSABLE_MEMORY_STAGE = zz_142; + assign decode_BYPASSABLE_MEMORY_STAGE = zz_48; assign execute_BRANCH_CALC = zz_15; - assign decode_SRC2 = zz_28; - assign decode_SRC_USE_SUB_LESS = zz_45; - assign memory_BRANCH_CALC = zz_139; - assign memory_BRANCH_DO = zz_199; - assign execute_PC = zz_192; - assign execute_RS1 = zz_171; + assign decode_SRC1 = zz_31; + assign decode_ALU_BITWISE_CTRL = zz_12; + assign zz_13 = zz_14; + assign memory_BRANCH_CALC = zz_141; + assign memory_BRANCH_DO = zz_202; + assign execute_PC = zz_194; + assign execute_RS1 = zz_175; assign execute_BRANCH_CTRL = zz_16; - assign decode_RS2_USE = zz_42; - assign decode_RS1_USE = zz_41; - assign execute_REGFILE_WRITE_VALID = zz_149; - assign execute_BYPASSABLE_EXECUTE_STAGE = zz_170; - assign memory_REGFILE_WRITE_VALID = zz_150; - assign memory_BYPASSABLE_MEMORY_STAGE = zz_142; - assign writeBack_REGFILE_WRITE_VALID = zz_151; - assign memory_SHIFT_RIGHT = zz_187; - always @ (memory_REGFILE_WRITE_DATA or memory_SHIFT_CTRL or zz_122 or memory_SHIFT_RIGHT) + assign decode_RS2_USE = zz_44; + assign decode_RS1_USE = zz_42; + assign execute_REGFILE_WRITE_VALID = zz_153; + assign execute_BYPASSABLE_EXECUTE_STAGE = zz_144; + assign memory_REGFILE_WRITE_VALID = zz_154; + assign memory_BYPASSABLE_MEMORY_STAGE = zz_143; + assign writeBack_REGFILE_WRITE_VALID = zz_155; + assign memory_SHIFT_RIGHT = zz_191; + always @ (memory_REGFILE_WRITE_DATA or memory_SHIFT_CTRL or zz_124 or memory_SHIFT_RIGHT) begin zz_18 = memory_REGFILE_WRITE_DATA; case(memory_SHIFT_CTRL) `ShiftCtrlEnum_binary_sequancial_SLL_1 : begin - zz_18 = zz_122; + zz_18 = zz_124; end `ShiftCtrlEnum_binary_sequancial_SRL_1, `ShiftCtrlEnum_binary_sequancial_SRA_1 : begin zz_18 = memory_SHIFT_RIGHT; @@ -656,8 +659,8 @@ module VexRiscv ( assign memory_SHIFT_CTRL = zz_19; assign execute_SHIFT_CTRL = zz_21; - assign execute_SRC_LESS_UNSIGNED = zz_148; - assign execute_SRC_USE_SUB_LESS = zz_137; + assign execute_SRC_LESS_UNSIGNED = zz_198; + assign execute_SRC_USE_SUB_LESS = zz_152; assign zz_25 = decode_PC; assign zz_26 = decode_RS2; assign decode_SRC2_CTRL = zz_27; @@ -666,8 +669,8 @@ module VexRiscv ( assign execute_SRC_ADD_SUB = zz_24; assign execute_SRC_LESS = zz_22; assign execute_ALU_CTRL = zz_32; - assign execute_SRC2 = zz_138; - assign execute_SRC1 = zz_179; + assign execute_SRC2 = zz_183; + assign execute_SRC1 = zz_140; assign execute_ALU_BITWISE_CTRL = zz_34; always @ (writeBack_RegFilePlugin_regFileWrite_valid) begin @@ -688,33 +691,35 @@ module VexRiscv ( assign decode_LEGAL_INSTRUCTION = zz_52; assign decode_INSTRUCTION_READY = zz_61; - assign writeBack_MEMORY_ENABLE = zz_166; - assign writeBack_MEMORY_ADDRESS_LOW = zz_189; - assign writeBack_MEMORY_READ_DATA = zz_169; - assign memory_INSTRUCTION = zz_162; - assign memory_MEMORY_ENABLE = zz_165; - assign execute_RS2 = zz_154; + assign writeBack_MEMORY_ENABLE = zz_171; + assign writeBack_MEMORY_ADDRESS_LOW = zz_146; + assign writeBack_MEMORY_READ_DATA = zz_174; + assign memory_REGFILE_WRITE_DATA = zz_199; + assign memory_ALIGNEMENT_FAULT = zz_161; + assign memory_INSTRUCTION = zz_167; + assign memory_MEMORY_ENABLE = zz_170; + assign execute_RS2 = zz_158; assign execute_SRC_ADD = zz_23; - assign execute_INSTRUCTION = zz_161; + assign execute_INSTRUCTION = zz_166; assign execute_ALIGNEMENT_FAULT = zz_60; - assign execute_MEMORY_ENABLE = zz_164; + assign execute_MEMORY_ENABLE = zz_169; assign zz_62 = fetch_INSTRUCTION; assign zz_65 = prefetch_PC; - always @ (memory_FORMAL_PC_NEXT or zz_81 or zz_82) + always @ (memory_FORMAL_PC_NEXT or zz_82 or zz_83) begin zz_66 = memory_FORMAL_PC_NEXT; - if(zz_81)begin - zz_66 = zz_82; + if(zz_82)begin + zz_66 = zz_83; end end assign prefetch_PC = zz_68; assign prefetch_PC_CALC_WITHOUT_JUMP = zz_69; - always @ (memory_FORMAL_HALT or memory_arbitration_isValid or memory_BRANCH_DO or zz_82 or memory_MEMORY_ENABLE or memory_INSTRUCTION or dBus_rsp_ready) + always @ (memory_FORMAL_HALT or zz_81 or memory_arbitration_isValid or memory_BRANCH_DO or zz_83 or memory_MEMORY_ENABLE or memory_INSTRUCTION or dBus_rsp_ready) begin zz_71 = memory_FORMAL_HALT; memory_arbitration_haltItself = 1'b0; - if(((memory_arbitration_isValid && memory_BRANCH_DO) && (zz_82[1 : 0] != (2'b00))))begin + if((zz_81 || ((memory_arbitration_isValid && memory_BRANCH_DO) && (zz_83[1 : 0] != (2'b00)))))begin zz_71 = 1'b1; memory_arbitration_haltItself = 1'b1; end @@ -724,7 +729,7 @@ module VexRiscv ( end assign zz_72 = execute_FORMAL_HALT; - always @ (decode_FORMAL_HALT or decodeExceptionPort_valid or decode_arbitration_isValid or zz_123 or zz_124) + always @ (decode_FORMAL_HALT or decodeExceptionPort_valid or decode_arbitration_isValid or zz_125 or zz_126) begin zz_73 = decode_FORMAL_HALT; decode_arbitration_haltItself = 1'b0; @@ -732,7 +737,7 @@ module VexRiscv ( zz_73 = 1'b1; decode_arbitration_haltItself = 1'b1; end - if((decode_arbitration_isValid && (zz_123 || zz_124)))begin + if((decode_arbitration_isValid && (zz_125 || zz_126)))begin decode_arbitration_haltItself = 1'b1; end end @@ -751,10 +756,10 @@ module VexRiscv ( assign zz_78 = writeBack_RS2_USE; assign zz_79 = writeBack_RS1_USE; assign zz_80 = writeBack_INSTRUCTION; - assign writeBack_PC = zz_194; - assign writeBack_INSTRUCTION = zz_163; - assign decode_PC = zz_191; - assign decode_INSTRUCTION = zz_160; + assign writeBack_PC = zz_196; + assign writeBack_INSTRUCTION = zz_168; + assign decode_PC = zz_193; + assign decode_INSTRUCTION = zz_165; always @ (iBus_cmd_ready or prefetch_IBusSimplePlugin_pendingCmd or iBus_rsp_ready) begin prefetch_arbitration_haltItself = 1'b0; @@ -766,10 +771,10 @@ module VexRiscv ( assign prefetch_arbitration_haltByOther = 1'b0; assign prefetch_arbitration_removeIt = 1'b0; assign prefetch_arbitration_flushAll = 1'b0; - always @ (fetch_arbitration_isValid or iBus_rsp_ready or zz_89) + always @ (fetch_arbitration_isValid or iBus_rsp_ready or zz_90) begin fetch_arbitration_haltItself = 1'b0; - if(((fetch_arbitration_isValid && (! iBus_rsp_ready)) && (! zz_89)))begin + if(((fetch_arbitration_isValid && (! iBus_rsp_ready)) && (! zz_90)))begin fetch_arbitration_haltItself = 1'b1; end end @@ -811,10 +816,10 @@ module VexRiscv ( end end - always @ (zz_81) + always @ (zz_82) begin execute_arbitration_flushAll = 1'b0; - if(zz_81)begin + if(zz_82)begin execute_arbitration_flushAll = 1'b1; end end @@ -840,18 +845,18 @@ module VexRiscv ( end assign writeBack_arbitration_flushAll = 1'b0; - always @ (writeBack_arbitration_isFiring or zz_88 or writeBack_FomalPlugin_haltFired) + always @ (writeBack_arbitration_isFiring or zz_89 or writeBack_FomalPlugin_haltFired) begin - zz_204 = writeBack_arbitration_isFiring; + zz_207 = writeBack_arbitration_isFiring; rvfi_trap = 1'b0; - zz_205 = 1'b0; - if(zz_88)begin - zz_204 = 1'b1; + zz_208 = 1'b0; + if(zz_89)begin + zz_207 = 1'b1; rvfi_trap = 1'b1; - zz_205 = 1'b1; + zz_208 = 1'b1; end if(writeBack_FomalPlugin_haltFired)begin - zz_204 = 1'b0; + zz_207 = 1'b0; end end @@ -906,9 +911,9 @@ module VexRiscv ( end end - assign zz_83 = 1'b0; + assign zz_84 = 1'b0; assign zz_70 = 1'b0; - assign prefetch_PcManagerSimplePlugin_pcBeforeJumps = (prefetch_PcManagerSimplePlugin_pcReg + zz_213); + assign prefetch_PcManagerSimplePlugin_pcBeforeJumps = (prefetch_PcManagerSimplePlugin_pcReg + zz_216); assign zz_69 = prefetch_PcManagerSimplePlugin_pcBeforeJumps; always @ (prefetch_PC_CALC_WITHOUT_JUMP or prefetch_PcManagerSimplePlugin_jump_pcLoad_valid or prefetch_PcManagerSimplePlugin_jump_pcLoad_payload or prefetch_arbitration_isFiring) begin @@ -923,64 +928,73 @@ module VexRiscv ( end end - assign prefetch_PcManagerSimplePlugin_jump_pcLoad_valid = zz_81; - assign prefetch_PcManagerSimplePlugin_jump_pcLoad_payload = zz_82; + assign prefetch_PcManagerSimplePlugin_jump_pcLoad_valid = zz_82; + assign prefetch_PcManagerSimplePlugin_jump_pcLoad_payload = zz_83; assign zz_68 = prefetch_PcManagerSimplePlugin_pc; assign zz_67 = (prefetch_PC + (32'b00000000000000000000000000000100)); - assign zz_206 = (((prefetch_arbitration_isValid && (! prefetch_arbitration_removeIt)) && (! prefetch_arbitration_isStuckByOthers)) && (! (prefetch_IBusSimplePlugin_pendingCmd && (! iBus_rsp_ready)))); + assign zz_209 = (((prefetch_arbitration_isValid && (! prefetch_arbitration_removeIt)) && (! prefetch_arbitration_isStuckByOthers)) && (! (prefetch_IBusSimplePlugin_pendingCmd && (! iBus_rsp_ready)))); assign iBus_cmd_payload_pc = zz_65; - always @ (iBus_rsp_inst or zz_89 or zz_90) + always @ (iBus_rsp_inst or zz_90 or zz_91) begin zz_64 = iBus_rsp_inst; - if(zz_89)begin - zz_64 = zz_90; + if(zz_90)begin + zz_64 = zz_91; end end assign zz_63 = (decode_arbitration_isStuck ? decode_INSTRUCTION : zz_62); assign zz_61 = 1'b1; - assign zz_60 = 1'b0; - assign zz_209 = ((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_removeIt)) && (! execute_ALIGNEMENT_FAULT)); - assign zz_210 = execute_INSTRUCTION[5]; - assign zz_208 = execute_SRC_ADD; - assign zz_207 = execute_INSTRUCTION[13 : 12]; - always @ (zz_207 or execute_RS2) + assign zz_60 = (((zz_210 == (2'b10)) && (zz_211[1 : 0] != (2'b00))) || ((zz_210 == (2'b01)) && (zz_211[0 : 0] != (1'b0)))); + assign zz_212 = ((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_removeIt)) && (! execute_ALIGNEMENT_FAULT)); + assign zz_213 = execute_INSTRUCTION[5]; + assign zz_211 = execute_SRC_ADD; + assign zz_210 = execute_INSTRUCTION[13 : 12]; + always @ (zz_210 or execute_RS2) begin - case(zz_207) + case(zz_210) 2'b00 : begin - zz_91 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + zz_92 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - zz_91 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + zz_92 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - zz_91 = execute_RS2[31 : 0]; + zz_92 = execute_RS2[31 : 0]; end endcase end - assign zz_211 = zz_91; - assign zz_59 = zz_208[1 : 0]; - always @ (zz_207) + assign zz_214 = zz_92; + assign zz_59 = zz_211[1 : 0]; + always @ (zz_210) begin - case(zz_207) + case(zz_210) 2'b00 : begin - execute_DBusSimplePlugin_formalMask = (4'b0001); + zz_93 = (4'b0001); end 2'b01 : begin - execute_DBusSimplePlugin_formalMask = (4'b0011); + zz_93 = (4'b0011); end default : begin - execute_DBusSimplePlugin_formalMask = (4'b1111); + zz_93 = (4'b1111); end endcase end - assign zz_58 = zz_208; - assign zz_57 = ((zz_209 && zz_210) ? execute_DBusSimplePlugin_formalMask : (4'b0000)); - assign zz_56 = ((zz_209 && (! zz_210)) ? execute_DBusSimplePlugin_formalMask : (4'b0000)); - assign zz_55 = zz_211; + assign execute_DBusSimplePlugin_formalMask = (zz_93 <<< zz_211[1 : 0]); + assign zz_58 = (zz_211 & (32'b11111111111111111111111111111100)); + assign zz_57 = ((zz_212 && zz_213) ? execute_DBusSimplePlugin_formalMask : (4'b0000)); + assign zz_56 = ((zz_212 && (! zz_213)) ? execute_DBusSimplePlugin_formalMask : (4'b0000)); + assign zz_55 = zz_214; assign zz_54 = dBus_rsp_data; + always @ (memory_ALIGNEMENT_FAULT or memory_arbitration_isValid or memory_MEMORY_ENABLE) + begin + zz_81 = memory_ALIGNEMENT_FAULT; + if((! (memory_arbitration_isValid && memory_MEMORY_ENABLE)))begin + zz_81 = 1'b0; + end + end + always @ (writeBack_MEMORY_READ_DATA or writeBack_MEMORY_ADDRESS_LOW) begin writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; @@ -999,37 +1013,7 @@ module VexRiscv ( endcase end - assign zz_92 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (zz_92 or writeBack_DBusSimplePlugin_rspShifted) - begin - zz_93[31] = zz_92; - zz_93[30] = zz_92; - zz_93[29] = zz_92; - zz_93[28] = zz_92; - zz_93[27] = zz_92; - zz_93[26] = zz_92; - zz_93[25] = zz_92; - zz_93[24] = zz_92; - zz_93[23] = zz_92; - zz_93[22] = zz_92; - zz_93[21] = zz_92; - zz_93[20] = zz_92; - zz_93[19] = zz_92; - zz_93[18] = zz_92; - zz_93[17] = zz_92; - zz_93[16] = zz_92; - zz_93[15] = zz_92; - zz_93[14] = zz_92; - zz_93[13] = zz_92; - zz_93[12] = zz_92; - zz_93[11] = zz_92; - zz_93[10] = zz_92; - zz_93[9] = zz_92; - zz_93[8] = zz_92; - zz_93[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; - end - - assign zz_94 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + assign zz_94 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); always @ (zz_94 or writeBack_DBusSimplePlugin_rspShifted) begin zz_95[31] = zz_94; @@ -1048,17 +1032,47 @@ module VexRiscv ( zz_95[18] = zz_94; zz_95[17] = zz_94; zz_95[16] = zz_94; - zz_95[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + zz_95[15] = zz_94; + zz_95[14] = zz_94; + zz_95[13] = zz_94; + zz_95[12] = zz_94; + zz_95[11] = zz_94; + zz_95[10] = zz_94; + zz_95[9] = zz_94; + zz_95[8] = zz_94; + zz_95[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; end - always @ (zz_212 or zz_93 or zz_95 or writeBack_DBusSimplePlugin_rspShifted) + assign zz_96 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (zz_96 or writeBack_DBusSimplePlugin_rspShifted) begin - case(zz_212) + zz_97[31] = zz_96; + zz_97[30] = zz_96; + zz_97[29] = zz_96; + zz_97[28] = zz_96; + zz_97[27] = zz_96; + zz_97[26] = zz_96; + zz_97[25] = zz_96; + zz_97[24] = zz_96; + zz_97[23] = zz_96; + zz_97[22] = zz_96; + zz_97[21] = zz_96; + zz_97[20] = zz_96; + zz_97[19] = zz_96; + zz_97[18] = zz_96; + zz_97[17] = zz_96; + zz_97[16] = zz_96; + zz_97[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @ (zz_215 or zz_95 or zz_97 or writeBack_DBusSimplePlugin_rspShifted) + begin + case(zz_215) 2'b00 : begin - writeBack_DBusSimplePlugin_rspFormated = zz_93; + writeBack_DBusSimplePlugin_rspFormated = zz_95; end 2'b01 : begin - writeBack_DBusSimplePlugin_rspFormated = zz_95; + writeBack_DBusSimplePlugin_rspFormated = zz_97; end default : begin writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; @@ -1066,52 +1080,52 @@ module VexRiscv ( endcase end - assign zz_53 = writeBack_DBusSimplePlugin_rspFormated; - assign zz_97 = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000000000)); - assign zz_98 = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); - assign zz_99 = ((decode_INSTRUCTION & (32'b00000000000000000000000000001000)) == (32'b00000000000000000000000000001000)); - assign zz_100 = ((decode_INSTRUCTION & (32'b00000000000000000000000001110000)) == (32'b00000000000000000000000000100000)); - assign zz_101 = ((decode_INSTRUCTION & (32'b00000000000000000000000000010100)) == (32'b00000000000000000000000000000100)); - assign zz_102 = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000001000000)); - assign zz_103 = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000000000)); - assign zz_104 = ((decode_INSTRUCTION & (32'b00000000000000000000000000010000)) == (32'b00000000000000000000000000010000)); - assign zz_96 = {({zz_99,zz_101} != (2'b00)),{(((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000100)) != (1'b0)),{({zz_99,{zz_104,{zz_98,{zz_97,((decode_INSTRUCTION & (32'b00000000000000000100000001000000)) == (32'b00000000000000000100000000000000))}}}} != (5'b00000)),{({zz_104,((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000100000))} != (2'b00)),{({((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000000)),{zz_103,((decode_INSTRUCTION & (32'b00000000000000000000000000011000)) == (32'b00000000000000000000000000000000))}} != (3'b000)),{({zz_102,{((decode_INSTRUCTION & (32'b00000000000000000000000000100100)) == (32'b00000000000000000000000000100000)),zz_100}} != (3'b000)),{(zz_103 != (1'b0)),{({zz_98,{((decode_INSTRUCTION & (32'b00000000000000000010000000100000)) == (32'b00000000000000000010000000100000)),{((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000010000)),{((decode_INSTRUCTION & (32'b00000000000000000001000000100000)) == (32'b00000000000000000000000000100000)),((decode_INSTRUCTION & (32'b00000000000000000001000000010000)) == (32'b00000000000000000000000000010000))}}}} != (5'b00000)),{({zz_102,{((decode_INSTRUCTION & (32'b01000000000000000000000000110000)) == (32'b01000000000000000000000000110000)),((decode_INSTRUCTION & (32'b00000000000000000010000000010100)) == (32'b00000000000000000010000000010000))}} != (3'b000)),{({((decode_INSTRUCTION & (32'b00000000000000000111000000010100)) == (32'b00000000000000000101000000010000)),((decode_INSTRUCTION & (32'b00000000000000000111000001100100)) == (32'b00000000000000000101000000100000))} != (2'b00)),{({((decode_INSTRUCTION & (32'b01000000000000000011000000010100)) == (32'b01000000000000000001000000010000)),{((decode_INSTRUCTION & (32'b01000000000000000100000001100100)) == (32'b01000000000000000100000000100000)),((decode_INSTRUCTION & (32'b00000000000000000111000000010100)) == (32'b00000000000000000001000000010000))}} != (3'b000)),{({((decode_INSTRUCTION & (32'b00000000000000000100000000000100)) == (32'b00000000000000000100000000000000)),((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100100))} != (2'b00)),{(((decode_INSTRUCTION & (32'b00000000000000000110000000000100)) == (32'b00000000000000000010000000000000)) != (1'b0)),{({((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000000000)),((decode_INSTRUCTION & (32'b00000000000000000101000000000000)) == (32'b00000000000000000001000000000000))} != (2'b00)),{({zz_99,zz_101} != (2'b00)),{(((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001000000)) != (1'b0)),{({((decode_INSTRUCTION & (32'b00000000000000000001000000000000)) == (32'b00000000000000000001000000000000)),zz_98} != (2'b00)),{({zz_98,((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000010000000000000))} != (2'b00)),{({zz_99,{zz_98,zz_100}} != (3'b000)),({zz_99,{zz_98,zz_97}} != (3'b000))}}}}}}}}}}}}}}}}}}}; + assign zz_53 = writeBack_MEMORY_READ_DATA; + assign zz_99 = ((decode_INSTRUCTION & (32'b00000000000000000000000000010100)) == (32'b00000000000000000000000000000100)); + assign zz_100 = ((decode_INSTRUCTION & (32'b00000000000000000000000000001000)) == (32'b00000000000000000000000000001000)); + assign zz_101 = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000001000000)); + assign zz_102 = ((decode_INSTRUCTION & (32'b00000000000000000000000000010000)) == (32'b00000000000000000000000000010000)); + assign zz_103 = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); + assign zz_104 = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000000000)); + assign zz_105 = ((decode_INSTRUCTION & (32'b00000000000000000000000001110000)) == (32'b00000000000000000000000000100000)); + assign zz_106 = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000000000)); + assign zz_98 = {({zz_100,zz_99} != (2'b00)),{(((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000100)) != (1'b0)),{({zz_100,{zz_102,{zz_103,{zz_106,((decode_INSTRUCTION & (32'b00000000000000000100000001000000)) == (32'b00000000000000000100000000000000))}}}} != (5'b00000)),{({zz_100,{zz_103,zz_105}} != (3'b000)),{({zz_100,{zz_103,zz_106}} != (3'b000)),{({zz_103,{((decode_INSTRUCTION & (32'b00000000000000000010000000100000)) == (32'b00000000000000000010000000100000)),{((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000010000)),{((decode_INSTRUCTION & (32'b00000000000000000001000000100000)) == (32'b00000000000000000000000000100000)),((decode_INSTRUCTION & (32'b00000000000000000001000000010000)) == (32'b00000000000000000000000000010000))}}}} != (5'b00000)),{({((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000000)),{zz_104,((decode_INSTRUCTION & (32'b00000000000000000000000000011000)) == (32'b00000000000000000000000000000000))}} != (3'b000)),{({((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000000000)),((decode_INSTRUCTION & (32'b00000000000000000101000000000000)) == (32'b00000000000000000001000000000000))} != (2'b00)),{({zz_101,{((decode_INSTRUCTION & (32'b00000000000000000000000000100100)) == (32'b00000000000000000000000000100000)),zz_105}} != (3'b000)),{(zz_104 != (1'b0)),{({((decode_INSTRUCTION & (32'b00000000000000000001000000000000)) == (32'b00000000000000000001000000000000)),zz_103} != (2'b00)),{({zz_103,((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000010000000000000))} != (2'b00)),{({((decode_INSTRUCTION & (32'b00000000000000000111000000010100)) == (32'b00000000000000000101000000010000)),((decode_INSTRUCTION & (32'b00000000000000000111000001100100)) == (32'b00000000000000000101000000100000))} != (2'b00)),{({((decode_INSTRUCTION & (32'b01000000000000000011000000010100)) == (32'b01000000000000000001000000010000)),{((decode_INSTRUCTION & (32'b01000000000000000100000001100100)) == (32'b01000000000000000100000000100000)),((decode_INSTRUCTION & (32'b00000000000000000111000000010100)) == (32'b00000000000000000001000000010000))}} != (3'b000)),{({zz_102,((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000100000))} != (2'b00)),{({zz_101,{((decode_INSTRUCTION & (32'b01000000000000000000000000110000)) == (32'b01000000000000000000000000110000)),((decode_INSTRUCTION & (32'b00000000000000000010000000010100)) == (32'b00000000000000000010000000010000))}} != (3'b000)),{({zz_100,zz_99} != (2'b00)),{(((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001000000)) != (1'b0)),{({((decode_INSTRUCTION & (32'b00000000000000000100000001100000)) == (32'b00000000000000000100000000100000)),{((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100100)),((decode_INSTRUCTION & (32'b00000000000000000100000000010100)) == (32'b00000000000000000100000000010000))}} != (3'b000)),(((decode_INSTRUCTION & (32'b00000000000000000110000000010100)) == (32'b00000000000000000010000000010000)) != (1'b0))}}}}}}}}}}}}}}}}}}}; assign zz_52 = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000001100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)),{((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & (32'b00000000000000000110000001011111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & (32'b00000000000000000101000001011111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & (32'b00000000000000000111000001111011)) == (32'b00000000000000000000000001100011)),{((decode_INSTRUCTION & (32'b11111110000000000000000001111111)) == (32'b00000000000000000000000000110011)),{((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & (32'b11111100000000000011000001111111)) == (32'b00000000000000000001000000010011)),{((decode_INSTRUCTION & (32'b10111110000000000111000001111111)) == (32'b00000000000000000101000000110011)),((decode_INSTRUCTION & (32'b10111110000000000111000001111111)) == (32'b00000000000000000000000000110011))}}}}}}}}}}}}}}} != (16'b0000000000000000)); - assign zz_105 = zz_96[1 : 0]; - assign zz_51 = zz_105; - assign zz_106 = zz_96[3 : 2]; - assign zz_50 = zz_106; - assign zz_107 = zz_96[5 : 4]; - assign zz_49 = zz_107; - assign zz_48 = zz_214[0]; - assign zz_108 = zz_96[8 : 7]; - assign zz_47 = zz_108; - assign zz_109 = zz_96[10 : 9]; - assign zz_46 = zz_109; - assign zz_45 = zz_215[0]; - assign zz_44 = zz_216[0]; - assign zz_43 = zz_217[0]; - assign zz_42 = zz_218[0]; - assign zz_41 = zz_219[0]; - assign zz_40 = zz_220[0]; - assign zz_39 = zz_221[0]; - assign zz_110 = zz_96[19 : 18]; - assign zz_38 = zz_110; + assign zz_107 = zz_98[1 : 0]; + assign zz_51 = zz_107; + assign zz_108 = zz_98[3 : 2]; + assign zz_50 = zz_108; + assign zz_49 = zz_217[0]; + assign zz_48 = zz_218[0]; + assign zz_109 = zz_98[7 : 6]; + assign zz_47 = zz_109; + assign zz_110 = zz_98[9 : 8]; + assign zz_46 = zz_110; + assign zz_45 = zz_219[0]; + assign zz_44 = zz_220[0]; + assign zz_43 = zz_221[0]; + assign zz_42 = zz_222[0]; + assign zz_41 = zz_223[0]; + assign zz_111 = zz_98[16 : 15]; + assign zz_40 = zz_111; + assign zz_39 = zz_224[0]; + assign zz_112 = zz_98[19 : 18]; + assign zz_38 = zz_112; assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = (4'b0010); assign decodeExceptionPort_payload_badAddr = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign zz_111 = 1'b1; - assign decode_RegFilePlugin_rs1Data = zz_202; - assign zz_112 = 1'b1; - assign decode_RegFilePlugin_rs2Data = zz_203; + assign zz_113 = 1'b1; + assign decode_RegFilePlugin_rs1Data = zz_205; + assign zz_114 = 1'b1; + assign decode_RegFilePlugin_rs2Data = zz_206; assign zz_37 = decode_RegFilePlugin_rs1Data; assign zz_36 = decode_RegFilePlugin_rs2Data; - always @ (zz_77 or writeBack_arbitration_isFiring or zz_113) + always @ (zz_77 or writeBack_arbitration_isFiring or zz_115) begin writeBack_RegFilePlugin_regFileWrite_valid = (zz_77 && writeBack_arbitration_isFiring); - if(zz_113)begin + if(zz_115)begin writeBack_RegFilePlugin_regFileWrite_valid = 1'b1; end end @@ -1140,60 +1154,35 @@ module VexRiscv ( begin case(execute_ALU_CTRL) `AluCtrlEnum_binary_sequancial_BITWISE : begin - zz_114 = execute_IntAluPlugin_bitwise; + zz_116 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_binary_sequancial_SLT_SLTU : begin - zz_114 = {31'd0, execute_SRC_LESS}; + zz_116 = {31'd0, execute_SRC_LESS}; end default : begin - zz_114 = execute_SRC_ADD_SUB; + zz_116 = execute_SRC_ADD_SUB; end endcase end - assign zz_33 = zz_114; + assign zz_33 = zz_116; always @ (decode_SRC1_CTRL or zz_29 or decode_INSTRUCTION) begin case(decode_SRC1_CTRL) `Src1CtrlEnum_binary_sequancial_RS : begin - zz_115 = zz_29; + zz_117 = zz_29; end `Src1CtrlEnum_binary_sequancial_FOUR : begin - zz_115 = (32'b00000000000000000000000000000100); + zz_117 = (32'b00000000000000000000000000000100); end default : begin - zz_115 = {decode_INSTRUCTION[31 : 12],(12'b000000000000)}; + zz_117 = {decode_INSTRUCTION[31 : 12],(12'b000000000000)}; end endcase end - assign zz_31 = zz_115; - assign zz_116 = zz_222[11]; - always @ (zz_116) - begin - zz_117[19] = zz_116; - zz_117[18] = zz_116; - zz_117[17] = zz_116; - zz_117[16] = zz_116; - zz_117[15] = zz_116; - zz_117[14] = zz_116; - zz_117[13] = zz_116; - zz_117[12] = zz_116; - zz_117[11] = zz_116; - zz_117[10] = zz_116; - zz_117[9] = zz_116; - zz_117[8] = zz_116; - zz_117[7] = zz_116; - zz_117[6] = zz_116; - zz_117[5] = zz_116; - zz_117[4] = zz_116; - zz_117[3] = zz_116; - zz_117[2] = zz_116; - zz_117[1] = zz_116; - zz_117[0] = zz_116; - end - - assign zz_118 = zz_223[11]; + assign zz_31 = zz_117; + assign zz_118 = zz_225[11]; always @ (zz_118) begin zz_119[19] = zz_118; @@ -1218,26 +1207,51 @@ module VexRiscv ( zz_119[0] = zz_118; end - always @ (decode_SRC2_CTRL or zz_26 or zz_117 or decode_INSTRUCTION or zz_119 or zz_25) + assign zz_120 = zz_226[11]; + always @ (zz_120) + begin + zz_121[19] = zz_120; + zz_121[18] = zz_120; + zz_121[17] = zz_120; + zz_121[16] = zz_120; + zz_121[15] = zz_120; + zz_121[14] = zz_120; + zz_121[13] = zz_120; + zz_121[12] = zz_120; + zz_121[11] = zz_120; + zz_121[10] = zz_120; + zz_121[9] = zz_120; + zz_121[8] = zz_120; + zz_121[7] = zz_120; + zz_121[6] = zz_120; + zz_121[5] = zz_120; + zz_121[4] = zz_120; + zz_121[3] = zz_120; + zz_121[2] = zz_120; + zz_121[1] = zz_120; + zz_121[0] = zz_120; + end + + always @ (decode_SRC2_CTRL or zz_26 or zz_119 or decode_INSTRUCTION or zz_121 or zz_25) begin case(decode_SRC2_CTRL) `Src2CtrlEnum_binary_sequancial_RS : begin - zz_120 = zz_26; + zz_122 = zz_26; end `Src2CtrlEnum_binary_sequancial_IMI : begin - zz_120 = {zz_117,decode_INSTRUCTION[31 : 20]}; + zz_122 = {zz_119,decode_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_binary_sequancial_IMS : begin - zz_120 = {zz_119,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}}; + zz_122 = {zz_121,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}}; end default : begin - zz_120 = zz_25; + zz_122 = zz_25; end endcase end - assign zz_28 = zz_120; - assign execute_SrcPlugin_addSub = zz_224; + assign zz_28 = zz_122; + assign execute_SrcPlugin_addSub = zz_227; assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign zz_24 = execute_SrcPlugin_addSub; assign zz_23 = execute_SrcPlugin_addSub; @@ -1245,191 +1259,166 @@ module VexRiscv ( assign execute_FullBarrielShifterPlugin_amplitude = execute_SRC2[4 : 0]; always @ (execute_SRC1) begin - zz_121[0] = execute_SRC1[31]; - zz_121[1] = execute_SRC1[30]; - zz_121[2] = execute_SRC1[29]; - zz_121[3] = execute_SRC1[28]; - zz_121[4] = execute_SRC1[27]; - zz_121[5] = execute_SRC1[26]; - zz_121[6] = execute_SRC1[25]; - zz_121[7] = execute_SRC1[24]; - zz_121[8] = execute_SRC1[23]; - zz_121[9] = execute_SRC1[22]; - zz_121[10] = execute_SRC1[21]; - zz_121[11] = execute_SRC1[20]; - zz_121[12] = execute_SRC1[19]; - zz_121[13] = execute_SRC1[18]; - zz_121[14] = execute_SRC1[17]; - zz_121[15] = execute_SRC1[16]; - zz_121[16] = execute_SRC1[15]; - zz_121[17] = execute_SRC1[14]; - zz_121[18] = execute_SRC1[13]; - zz_121[19] = execute_SRC1[12]; - zz_121[20] = execute_SRC1[11]; - zz_121[21] = execute_SRC1[10]; - zz_121[22] = execute_SRC1[9]; - zz_121[23] = execute_SRC1[8]; - zz_121[24] = execute_SRC1[7]; - zz_121[25] = execute_SRC1[6]; - zz_121[26] = execute_SRC1[5]; - zz_121[27] = execute_SRC1[4]; - zz_121[28] = execute_SRC1[3]; - zz_121[29] = execute_SRC1[2]; - zz_121[30] = execute_SRC1[1]; - zz_121[31] = execute_SRC1[0]; + zz_123[0] = execute_SRC1[31]; + zz_123[1] = execute_SRC1[30]; + zz_123[2] = execute_SRC1[29]; + zz_123[3] = execute_SRC1[28]; + zz_123[4] = execute_SRC1[27]; + zz_123[5] = execute_SRC1[26]; + zz_123[6] = execute_SRC1[25]; + zz_123[7] = execute_SRC1[24]; + zz_123[8] = execute_SRC1[23]; + zz_123[9] = execute_SRC1[22]; + zz_123[10] = execute_SRC1[21]; + zz_123[11] = execute_SRC1[20]; + zz_123[12] = execute_SRC1[19]; + zz_123[13] = execute_SRC1[18]; + zz_123[14] = execute_SRC1[17]; + zz_123[15] = execute_SRC1[16]; + zz_123[16] = execute_SRC1[15]; + zz_123[17] = execute_SRC1[14]; + zz_123[18] = execute_SRC1[13]; + zz_123[19] = execute_SRC1[12]; + zz_123[20] = execute_SRC1[11]; + zz_123[21] = execute_SRC1[10]; + zz_123[22] = execute_SRC1[9]; + zz_123[23] = execute_SRC1[8]; + zz_123[24] = execute_SRC1[7]; + zz_123[25] = execute_SRC1[6]; + zz_123[26] = execute_SRC1[5]; + zz_123[27] = execute_SRC1[4]; + zz_123[28] = execute_SRC1[3]; + zz_123[29] = execute_SRC1[2]; + zz_123[30] = execute_SRC1[1]; + zz_123[31] = execute_SRC1[0]; end - assign execute_FullBarrielShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequancial_SLL_1) ? zz_121 : execute_SRC1); - assign zz_20 = zz_233; + assign execute_FullBarrielShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequancial_SLL_1) ? zz_123 : execute_SRC1); + assign zz_20 = zz_236; always @ (memory_SHIFT_RIGHT) begin - zz_122[0] = memory_SHIFT_RIGHT[31]; - zz_122[1] = memory_SHIFT_RIGHT[30]; - zz_122[2] = memory_SHIFT_RIGHT[29]; - zz_122[3] = memory_SHIFT_RIGHT[28]; - zz_122[4] = memory_SHIFT_RIGHT[27]; - zz_122[5] = memory_SHIFT_RIGHT[26]; - zz_122[6] = memory_SHIFT_RIGHT[25]; - zz_122[7] = memory_SHIFT_RIGHT[24]; - zz_122[8] = memory_SHIFT_RIGHT[23]; - zz_122[9] = memory_SHIFT_RIGHT[22]; - zz_122[10] = memory_SHIFT_RIGHT[21]; - zz_122[11] = memory_SHIFT_RIGHT[20]; - zz_122[12] = memory_SHIFT_RIGHT[19]; - zz_122[13] = memory_SHIFT_RIGHT[18]; - zz_122[14] = memory_SHIFT_RIGHT[17]; - zz_122[15] = memory_SHIFT_RIGHT[16]; - zz_122[16] = memory_SHIFT_RIGHT[15]; - zz_122[17] = memory_SHIFT_RIGHT[14]; - zz_122[18] = memory_SHIFT_RIGHT[13]; - zz_122[19] = memory_SHIFT_RIGHT[12]; - zz_122[20] = memory_SHIFT_RIGHT[11]; - zz_122[21] = memory_SHIFT_RIGHT[10]; - zz_122[22] = memory_SHIFT_RIGHT[9]; - zz_122[23] = memory_SHIFT_RIGHT[8]; - zz_122[24] = memory_SHIFT_RIGHT[7]; - zz_122[25] = memory_SHIFT_RIGHT[6]; - zz_122[26] = memory_SHIFT_RIGHT[5]; - zz_122[27] = memory_SHIFT_RIGHT[4]; - zz_122[28] = memory_SHIFT_RIGHT[3]; - zz_122[29] = memory_SHIFT_RIGHT[2]; - zz_122[30] = memory_SHIFT_RIGHT[1]; - zz_122[31] = memory_SHIFT_RIGHT[0]; + zz_124[0] = memory_SHIFT_RIGHT[31]; + zz_124[1] = memory_SHIFT_RIGHT[30]; + zz_124[2] = memory_SHIFT_RIGHT[29]; + zz_124[3] = memory_SHIFT_RIGHT[28]; + zz_124[4] = memory_SHIFT_RIGHT[27]; + zz_124[5] = memory_SHIFT_RIGHT[26]; + zz_124[6] = memory_SHIFT_RIGHT[25]; + zz_124[7] = memory_SHIFT_RIGHT[24]; + zz_124[8] = memory_SHIFT_RIGHT[23]; + zz_124[9] = memory_SHIFT_RIGHT[22]; + zz_124[10] = memory_SHIFT_RIGHT[21]; + zz_124[11] = memory_SHIFT_RIGHT[20]; + zz_124[12] = memory_SHIFT_RIGHT[19]; + zz_124[13] = memory_SHIFT_RIGHT[18]; + zz_124[14] = memory_SHIFT_RIGHT[17]; + zz_124[15] = memory_SHIFT_RIGHT[16]; + zz_124[16] = memory_SHIFT_RIGHT[15]; + zz_124[17] = memory_SHIFT_RIGHT[14]; + zz_124[18] = memory_SHIFT_RIGHT[13]; + zz_124[19] = memory_SHIFT_RIGHT[12]; + zz_124[20] = memory_SHIFT_RIGHT[11]; + zz_124[21] = memory_SHIFT_RIGHT[10]; + zz_124[22] = memory_SHIFT_RIGHT[9]; + zz_124[23] = memory_SHIFT_RIGHT[8]; + zz_124[24] = memory_SHIFT_RIGHT[7]; + zz_124[25] = memory_SHIFT_RIGHT[6]; + zz_124[26] = memory_SHIFT_RIGHT[5]; + zz_124[27] = memory_SHIFT_RIGHT[4]; + zz_124[28] = memory_SHIFT_RIGHT[3]; + zz_124[29] = memory_SHIFT_RIGHT[2]; + zz_124[30] = memory_SHIFT_RIGHT[1]; + zz_124[31] = memory_SHIFT_RIGHT[0]; end - always @ (zz_125 or zz_126 or decode_INSTRUCTION or writeBack_arbitration_isValid or writeBack_REGFILE_WRITE_VALID or writeBack_INSTRUCTION or memory_arbitration_isValid or memory_REGFILE_WRITE_VALID or memory_BYPASSABLE_MEMORY_STAGE or memory_INSTRUCTION or execute_arbitration_isValid or execute_REGFILE_WRITE_VALID or execute_BYPASSABLE_EXECUTE_STAGE or execute_INSTRUCTION or decode_RS1_USE or decode_RS2_USE) + always @ (zz_127 or zz_128 or decode_INSTRUCTION or writeBack_arbitration_isValid or writeBack_REGFILE_WRITE_VALID or writeBack_INSTRUCTION or memory_arbitration_isValid or memory_REGFILE_WRITE_VALID or memory_BYPASSABLE_MEMORY_STAGE or memory_INSTRUCTION or execute_arbitration_isValid or execute_REGFILE_WRITE_VALID or execute_BYPASSABLE_EXECUTE_STAGE or execute_INSTRUCTION or decode_RS1_USE or decode_RS2_USE) begin - zz_123 = 1'b0; - zz_124 = 1'b0; - if(zz_125)begin - if((zz_126 == decode_INSTRUCTION[19 : 15]))begin - zz_123 = 1'b1; + zz_125 = 1'b0; + zz_126 = 1'b0; + if(zz_127)begin + if((zz_128 == decode_INSTRUCTION[19 : 15]))begin + zz_125 = 1'b1; end - if((zz_126 == decode_INSTRUCTION[24 : 20]))begin - zz_124 = 1'b1; + if((zz_128 == decode_INSTRUCTION[24 : 20]))begin + zz_126 = 1'b1; end end if((writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID))begin if((1'b1 || (! 1'b1)))begin if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - zz_123 = 1'b1; + zz_125 = 1'b1; end if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - zz_124 = 1'b1; + zz_126 = 1'b1; end end end if((memory_arbitration_isValid && memory_REGFILE_WRITE_VALID))begin if((1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)))begin if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - zz_123 = 1'b1; + zz_125 = 1'b1; end if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - zz_124 = 1'b1; + zz_126 = 1'b1; end end end if((execute_arbitration_isValid && execute_REGFILE_WRITE_VALID))begin if((1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)))begin if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - zz_123 = 1'b1; + zz_125 = 1'b1; end if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - zz_124 = 1'b1; + zz_126 = 1'b1; end end end if((! decode_RS1_USE))begin - zz_123 = 1'b0; + zz_125 = 1'b0; end if((! decode_RS2_USE))begin - zz_124 = 1'b0; + zz_126 = 1'b0; end end assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign zz_127 = execute_INSTRUCTION[14 : 12]; - always @ (zz_127 or execute_BranchPlugin_eq or execute_SRC_LESS) + assign zz_129 = execute_INSTRUCTION[14 : 12]; + always @ (zz_129 or execute_BranchPlugin_eq or execute_SRC_LESS) begin - if((zz_127 == (3'b000))) begin - zz_128 = execute_BranchPlugin_eq; - end else if((zz_127 == (3'b001))) begin - zz_128 = (! execute_BranchPlugin_eq); - end else if((((zz_127 & (3'b101)) == (3'b101)))) begin - zz_128 = (! execute_SRC_LESS); + if((zz_129 == (3'b000))) begin + zz_130 = execute_BranchPlugin_eq; + end else if((zz_129 == (3'b001))) begin + zz_130 = (! execute_BranchPlugin_eq); + end else if((((zz_129 & (3'b101)) == (3'b101)))) begin + zz_130 = (! execute_SRC_LESS); end else begin - zz_128 = execute_SRC_LESS; + zz_130 = execute_SRC_LESS; end end - always @ (execute_BRANCH_CTRL or zz_128) + always @ (execute_BRANCH_CTRL or zz_130) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_binary_sequancial_INC : begin - zz_129 = 1'b0; + zz_131 = 1'b0; end `BranchCtrlEnum_binary_sequancial_JAL : begin - zz_129 = 1'b1; + zz_131 = 1'b1; end `BranchCtrlEnum_binary_sequancial_JALR : begin - zz_129 = 1'b1; + zz_131 = 1'b1; end default : begin - zz_129 = zz_128; + zz_131 = zz_130; end endcase end - assign zz_17 = zz_129; + assign zz_17 = zz_131; assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequancial_JALR) ? execute_RS1 : execute_PC); - assign zz_130 = zz_235[19]; - always @ (zz_130) - begin - zz_131[10] = zz_130; - zz_131[9] = zz_130; - zz_131[8] = zz_130; - zz_131[7] = zz_130; - zz_131[6] = zz_130; - zz_131[5] = zz_130; - zz_131[4] = zz_130; - zz_131[3] = zz_130; - zz_131[2] = zz_130; - zz_131[1] = zz_130; - zz_131[0] = zz_130; - end - - assign zz_132 = zz_236[11]; + assign zz_132 = zz_238[19]; always @ (zz_132) begin - zz_133[19] = zz_132; - zz_133[18] = zz_132; - zz_133[17] = zz_132; - zz_133[16] = zz_132; - zz_133[15] = zz_132; - zz_133[14] = zz_132; - zz_133[13] = zz_132; - zz_133[12] = zz_132; - zz_133[11] = zz_132; zz_133[10] = zz_132; zz_133[9] = zz_132; zz_133[8] = zz_132; @@ -1443,9 +1432,10 @@ module VexRiscv ( zz_133[0] = zz_132; end - assign zz_134 = zz_237[11]; + assign zz_134 = zz_239[11]; always @ (zz_134) begin + zz_135[19] = zz_134; zz_135[18] = zz_134; zz_135[17] = zz_134; zz_135[16] = zz_134; @@ -1467,42 +1457,66 @@ module VexRiscv ( zz_135[0] = zz_134; end - always @ (execute_BRANCH_CTRL or zz_131 or execute_INSTRUCTION or zz_133 or zz_135) + assign zz_136 = zz_240[11]; + always @ (zz_136) + begin + zz_137[18] = zz_136; + zz_137[17] = zz_136; + zz_137[16] = zz_136; + zz_137[15] = zz_136; + zz_137[14] = zz_136; + zz_137[13] = zz_136; + zz_137[12] = zz_136; + zz_137[11] = zz_136; + zz_137[10] = zz_136; + zz_137[9] = zz_136; + zz_137[8] = zz_136; + zz_137[7] = zz_136; + zz_137[6] = zz_136; + zz_137[5] = zz_136; + zz_137[4] = zz_136; + zz_137[3] = zz_136; + zz_137[2] = zz_136; + zz_137[1] = zz_136; + zz_137[0] = zz_136; + end + + always @ (execute_BRANCH_CTRL or zz_133 or execute_INSTRUCTION or zz_135 or zz_137) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_binary_sequancial_JAL : begin - zz_136 = {{zz_131,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + zz_138 = {{zz_133,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; end `BranchCtrlEnum_binary_sequancial_JALR : begin - zz_136 = {zz_133,execute_INSTRUCTION[31 : 20]}; + zz_138 = {zz_135,execute_INSTRUCTION[31 : 20]}; end default : begin - zz_136 = {{zz_135,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + zz_138 = {{zz_137,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; end endcase end - assign execute_BranchPlugin_branch_src2 = zz_136; + assign execute_BranchPlugin_branch_src2 = zz_138; assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign zz_15 = {execute_BranchPlugin_branchAdder[31 : 1],((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequancial_JALR) ? 1'b0 : execute_BranchPlugin_branchAdder[0])}; - assign zz_81 = (memory_arbitration_isFiring && memory_BRANCH_DO); - assign zz_82 = memory_BRANCH_CALC; - assign zz_14 = decode_ALU_CTRL; - assign zz_12 = zz_47; - assign zz_32 = zz_140; - assign zz_27 = zz_51; + assign zz_82 = (memory_arbitration_isFiring && memory_BRANCH_DO); + assign zz_83 = memory_BRANCH_CALC; + assign zz_14 = decode_ALU_BITWISE_CTRL; + assign zz_12 = zz_46; + assign zz_34 = zz_139; + assign zz_27 = zz_40; assign zz_30 = zz_38; assign zz_11 = decode_SHIFT_CTRL; assign zz_8 = execute_SHIFT_CTRL; - assign zz_9 = zz_46; - assign zz_21 = zz_185; - assign zz_19 = zz_186; - assign zz_6 = decode_ALU_BITWISE_CTRL; - assign zz_4 = zz_50; - assign zz_34 = zz_195; + assign zz_9 = zz_47; + assign zz_21 = zz_189; + assign zz_19 = zz_190; + assign zz_6 = decode_ALU_CTRL; + assign zz_4 = zz_51; + assign zz_32 = zz_197; assign zz_3 = decode_BRANCH_CTRL; - assign zz_1 = zz_49; - assign zz_16 = zz_198; + assign zz_1 = zz_50; + assign zz_16 = zz_201; assign prefetch_arbitration_isFlushed = (((((prefetch_arbitration_flushAll || fetch_arbitration_flushAll) || decode_arbitration_flushAll) || execute_arbitration_flushAll) || memory_arbitration_flushAll) || writeBack_arbitration_flushAll); assign fetch_arbitration_isFlushed = ((((fetch_arbitration_flushAll || decode_arbitration_flushAll) || execute_arbitration_flushAll) || memory_arbitration_flushAll) || writeBack_arbitration_flushAll); assign decode_arbitration_isFlushed = (((decode_arbitration_flushAll || execute_arbitration_flushAll) || memory_arbitration_flushAll) || writeBack_arbitration_flushAll); @@ -1537,30 +1551,30 @@ module VexRiscv ( memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; writeBack_FomalPlugin_order <= (64'b0000000000000000000000000000000000000000000000000000000000000000); - zz_84 <= zz_83; - zz_85 <= zz_83; - zz_86 <= zz_83; - zz_87 <= zz_83; - zz_88 <= zz_83; + zz_85 <= zz_84; + zz_86 <= zz_84; + zz_87 <= zz_84; + zz_88 <= zz_84; + zz_89 <= zz_84; writeBack_FomalPlugin_haltFired <= 1'b0; prefetch_PcManagerSimplePlugin_pcReg <= (32'b00000000000000000000000000000000); prefetch_PcManagerSimplePlugin_inc <= 1'b0; prefetch_IBusSimplePlugin_pendingCmd <= 1'b0; - zz_89 <= 1'b0; - zz_113 <= 1'b1; - zz_125 <= 1'b0; - zz_197 <= (32'b00000000000000000000000000000000); - zz_163 <= (32'b00000000000000000000000000000000); + zz_90 <= 1'b0; + zz_115 <= 1'b1; + zz_127 <= 1'b0; + zz_200 <= (32'b00000000000000000000000000000000); + zz_168 <= (32'b00000000000000000000000000000000); end else begin if(writeBack_arbitration_isFiring)begin writeBack_FomalPlugin_order <= (writeBack_FomalPlugin_order + (64'b0000000000000000000000000000000000000000000000000000000000000001)); end - zz_84 <= writeBack_FomalPlugin_haltRequest; - zz_85 <= zz_84; + zz_85 <= writeBack_FomalPlugin_haltRequest; zz_86 <= zz_85; zz_87 <= zz_86; zz_88 <= zz_87; - if((zz_204 && zz_205))begin + zz_89 <= zz_88; + if((zz_207 && zz_208))begin writeBack_FomalPlugin_haltFired <= 1'b1; end prefetch_arbitration_isValid <= 1'b1; @@ -1576,22 +1590,22 @@ module VexRiscv ( if(iBus_rsp_ready)begin prefetch_IBusSimplePlugin_pendingCmd <= 1'b0; end - if((zz_206 && iBus_cmd_ready))begin + if((zz_209 && iBus_cmd_ready))begin prefetch_IBusSimplePlugin_pendingCmd <= 1'b1; end if(iBus_rsp_ready)begin - zz_89 <= 1'b1; + zz_90 <= 1'b1; end if((! fetch_arbitration_isStuck))begin - zz_89 <= 1'b0; + zz_90 <= 1'b0; end - zz_113 <= 1'b0; - zz_125 <= (zz_77 && writeBack_arbitration_isFiring); + zz_115 <= 1'b0; + zz_127 <= (zz_77 && writeBack_arbitration_isFiring); if((! writeBack_arbitration_isStuck))begin - zz_163 <= memory_INSTRUCTION; + zz_168 <= memory_INSTRUCTION; end if((! writeBack_arbitration_isStuck))begin - zz_197 <= zz_18; + zz_200 <= zz_18; end if(((! fetch_arbitration_isStuck) || fetch_arbitration_removeIt))begin fetch_arbitration_isValid <= 1'b0; @@ -1628,8 +1642,8 @@ module VexRiscv ( always @ (posedge clk) begin - if((! zz_89))begin - zz_90 <= iBus_rsp_inst; + if((! zz_90))begin + zz_91 <= iBus_rsp_inst; end if (!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin $display("ERROR DBusSimplePlugin doesn't allow memory stage stall when read happend"); @@ -1637,195 +1651,198 @@ module VexRiscv ( if (!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_INSTRUCTION[5])) && writeBack_arbitration_isStuck))) begin $display("ERROR DBusSimplePlugin doesn't allow memory stage stall when read happend"); end - zz_126 <= zz_80[11 : 7]; + zz_128 <= zz_80[11 : 7]; if((! execute_arbitration_isStuck))begin - zz_137 <= decode_SRC_USE_SUB_LESS; + zz_139 <= zz_13; end if((! execute_arbitration_isStuck))begin - zz_138 <= decode_SRC2; + zz_140 <= decode_SRC1; end if((! memory_arbitration_isStuck))begin - zz_139 <= execute_BRANCH_CALC; + zz_141 <= execute_BRANCH_CALC; end if((! execute_arbitration_isStuck))begin - zz_140 <= zz_13; + zz_142 <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + zz_143 <= execute_BYPASSABLE_MEMORY_STAGE; end if((! execute_arbitration_isStuck))begin - zz_141 <= decode_BYPASSABLE_MEMORY_STAGE; + zz_144 <= decode_BYPASSABLE_EXECUTE_STAGE; end if((! memory_arbitration_isStuck))begin - zz_142 <= execute_BYPASSABLE_MEMORY_STAGE; + zz_145 <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + zz_146 <= memory_MEMORY_ADDRESS_LOW; end if((! fetch_arbitration_isStuck))begin - zz_143 <= zz_75; + zz_147 <= zz_75; end if((! decode_arbitration_isStuck))begin - zz_144 <= zz_74; + zz_148 <= zz_74; end if((! execute_arbitration_isStuck))begin - zz_145 <= zz_73; + zz_149 <= zz_73; end if((! memory_arbitration_isStuck))begin - zz_146 <= zz_72; + zz_150 <= zz_72; end if((! writeBack_arbitration_isStuck))begin - zz_147 <= zz_71; + zz_151 <= zz_71; end if((! execute_arbitration_isStuck))begin - zz_148 <= decode_SRC_LESS_UNSIGNED; + zz_152 <= decode_SRC_USE_SUB_LESS; end if((! execute_arbitration_isStuck))begin - zz_149 <= decode_REGFILE_WRITE_VALID; + zz_153 <= decode_REGFILE_WRITE_VALID; end if((! memory_arbitration_isStuck))begin - zz_150 <= execute_REGFILE_WRITE_VALID; + zz_154 <= execute_REGFILE_WRITE_VALID; end if((! writeBack_arbitration_isStuck))begin - zz_151 <= memory_REGFILE_WRITE_VALID; + zz_155 <= memory_REGFILE_WRITE_VALID; end if((! memory_arbitration_isStuck))begin - zz_152 <= execute_FORMAL_MEM_WMASK; + zz_156 <= execute_FORMAL_MEM_WMASK; end if((! writeBack_arbitration_isStuck))begin - zz_153 <= memory_FORMAL_MEM_WMASK; + zz_157 <= memory_FORMAL_MEM_WMASK; end if((! execute_arbitration_isStuck))begin - zz_154 <= zz_26; + zz_158 <= zz_26; end if((! memory_arbitration_isStuck))begin - zz_155 <= execute_RS2; + zz_159 <= execute_RS2; end if((! writeBack_arbitration_isStuck))begin - zz_156 <= memory_RS2; + zz_160 <= memory_RS2; + end + if((! memory_arbitration_isStuck))begin + zz_161 <= execute_ALIGNEMENT_FAULT; end if((! execute_arbitration_isStuck))begin - zz_157 <= decode_RS1_USE; + zz_162 <= decode_RS1_USE; end if((! memory_arbitration_isStuck))begin - zz_158 <= execute_RS1_USE; + zz_163 <= execute_RS1_USE; end if((! writeBack_arbitration_isStuck))begin - zz_159 <= memory_RS1_USE; + zz_164 <= memory_RS1_USE; end if((! decode_arbitration_isStuck))begin - zz_160 <= zz_62; + zz_165 <= zz_62; end if((! execute_arbitration_isStuck))begin - zz_161 <= decode_INSTRUCTION; + zz_166 <= decode_INSTRUCTION; end if((! memory_arbitration_isStuck))begin - zz_162 <= execute_INSTRUCTION; + zz_167 <= execute_INSTRUCTION; end if((! execute_arbitration_isStuck))begin - zz_164 <= decode_MEMORY_ENABLE; + zz_169 <= decode_MEMORY_ENABLE; end if((! memory_arbitration_isStuck))begin - zz_165 <= execute_MEMORY_ENABLE; + zz_170 <= execute_MEMORY_ENABLE; end if((! writeBack_arbitration_isStuck))begin - zz_166 <= memory_MEMORY_ENABLE; + zz_171 <= memory_MEMORY_ENABLE; end if((! memory_arbitration_isStuck))begin - zz_167 <= execute_FORMAL_MEM_WDATA; + zz_172 <= execute_FORMAL_MEM_WDATA; end if((! writeBack_arbitration_isStuck))begin - zz_168 <= memory_FORMAL_MEM_WDATA; + zz_173 <= memory_FORMAL_MEM_WDATA; end if((! writeBack_arbitration_isStuck))begin - zz_169 <= memory_MEMORY_READ_DATA; - end - if((! execute_arbitration_isStuck))begin - zz_170 <= decode_BYPASSABLE_EXECUTE_STAGE; + zz_174 <= memory_MEMORY_READ_DATA; end if((! execute_arbitration_isStuck))begin - zz_171 <= zz_29; + zz_175 <= zz_29; end if((! memory_arbitration_isStuck))begin - zz_172 <= execute_RS1; + zz_176 <= execute_RS1; end if((! writeBack_arbitration_isStuck))begin - zz_173 <= memory_RS1; + zz_177 <= memory_RS1; end if((! execute_arbitration_isStuck))begin - zz_174 <= decode_RS2_USE; + zz_178 <= decode_RS2_USE; end if((! memory_arbitration_isStuck))begin - zz_175 <= execute_RS2_USE; + zz_179 <= execute_RS2_USE; end if((! writeBack_arbitration_isStuck))begin - zz_176 <= memory_RS2_USE; + zz_180 <= memory_RS2_USE; end if((! memory_arbitration_isStuck))begin - zz_177 <= execute_FORMAL_MEM_RMASK; + zz_181 <= execute_FORMAL_MEM_RMASK; end if((! writeBack_arbitration_isStuck))begin - zz_178 <= memory_FORMAL_MEM_RMASK; + zz_182 <= memory_FORMAL_MEM_RMASK; end if((! execute_arbitration_isStuck))begin - zz_179 <= decode_SRC1; + zz_183 <= decode_SRC2; end if((! fetch_arbitration_isStuck))begin - zz_180 <= prefetch_FORMAL_PC_NEXT; + zz_184 <= prefetch_FORMAL_PC_NEXT; end if((! decode_arbitration_isStuck))begin - zz_181 <= fetch_FORMAL_PC_NEXT; + zz_185 <= fetch_FORMAL_PC_NEXT; end if((! execute_arbitration_isStuck))begin - zz_182 <= decode_FORMAL_PC_NEXT; + zz_186 <= decode_FORMAL_PC_NEXT; end if((! memory_arbitration_isStuck))begin - zz_183 <= execute_FORMAL_PC_NEXT; + zz_187 <= execute_FORMAL_PC_NEXT; end if((! writeBack_arbitration_isStuck))begin - zz_184 <= zz_66; + zz_188 <= zz_66; end if((! execute_arbitration_isStuck))begin - zz_185 <= zz_10; + zz_189 <= zz_10; end if((! memory_arbitration_isStuck))begin - zz_186 <= zz_7; + zz_190 <= zz_7; end if((! memory_arbitration_isStuck))begin - zz_187 <= execute_SHIFT_RIGHT; - end - if((! memory_arbitration_isStuck))begin - zz_188 <= execute_MEMORY_ADDRESS_LOW; - end - if((! writeBack_arbitration_isStuck))begin - zz_189 <= memory_MEMORY_ADDRESS_LOW; + zz_191 <= execute_SHIFT_RIGHT; end if((! fetch_arbitration_isStuck))begin - zz_190 <= zz_65; + zz_192 <= zz_65; end if((! decode_arbitration_isStuck))begin - zz_191 <= fetch_PC; + zz_193 <= fetch_PC; end if((! execute_arbitration_isStuck))begin - zz_192 <= zz_25; + zz_194 <= zz_25; end if((! memory_arbitration_isStuck))begin - zz_193 <= execute_PC; + zz_195 <= execute_PC; end if((! writeBack_arbitration_isStuck))begin - zz_194 <= memory_PC; + zz_196 <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + zz_197 <= zz_5; end if((! execute_arbitration_isStuck))begin - zz_195 <= zz_5; + zz_198 <= decode_SRC_LESS_UNSIGNED; end if((! memory_arbitration_isStuck))begin - zz_196 <= execute_REGFILE_WRITE_DATA; + zz_199 <= execute_REGFILE_WRITE_DATA; end if((! execute_arbitration_isStuck))begin - zz_198 <= zz_2; + zz_201 <= zz_2; end if((! memory_arbitration_isStuck))begin - zz_199 <= execute_BRANCH_DO; + zz_202 <= execute_BRANCH_DO; end if((! memory_arbitration_isStuck))begin - zz_200 <= execute_FORMAL_MEM_ADDR; + zz_203 <= execute_FORMAL_MEM_ADDR; end if((! writeBack_arbitration_isStuck))begin - zz_201 <= memory_FORMAL_MEM_ADDR; + zz_204 <= memory_FORMAL_MEM_ADDR; end if (!(prefetch_arbitration_removeIt == 1'b0)) begin $display("ERROR removeIt should never be asserted on this stage"); diff --git a/cores/VexRiscv/checks.cfg b/cores/VexRiscv/checks.cfg index b969482..7191841 100644 --- a/cores/VexRiscv/checks.cfg +++ b/cores/VexRiscv/checks.cfg @@ -11,8 +11,8 @@ unique 1 10 30 causal 10 30 [defines] -//`define RISCV_FORMAL_ALIGNED_MEM -//`define RISCV_FORMAL_TRAP_ALIGNED_MEM +`define RISCV_FORMAL_ALIGNED_MEM +`define RISCV_FORMAL_TRAP_ALIGNED_MEM //`define RISCV_FORMAL_TRAP_ALIGNED_INSN `define RISCV_FORMAL_ALTOPS `define DEBUGNETS diff --git a/cores/VexRiscv/dmemcheck.sby b/cores/VexRiscv/dmemcheck.sby new file mode 100644 index 0000000..9d0d49b --- /dev/null +++ b/cores/VexRiscv/dmemcheck.sby @@ -0,0 +1,21 @@ +[options] +mode bmc +append 0 +tbtop testbench.uut +depth 22 + +[engines] +smtbmc --presat --unroll boolector + +[script] +read_verilog -sv dmemcheck.sv +read_verilog /home/spinalvm/hdl/formal/riscv-formal/cores/VexRiscv/VexRiscv.v +prep -nordff -top testbench + +[files] +dmemcheck.sv +/home/spinalvm/hdl/formal/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh +/home/spinalvm/hdl/formal/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv +/home/spinalvm/hdl/formal/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv +/home/spinalvm/hdl/formal/riscv-formal/cores/picorv32/../../checks/rvfi_dmem_check.sv + diff --git a/cores/VexRiscv/dmemcheck.sv b/cores/VexRiscv/dmemcheck.sv new file mode 100644 index 0000000..3f269ec --- /dev/null +++ b/cores/VexRiscv/dmemcheck.sv @@ -0,0 +1,116 @@ +`define RISCV_FORMAL +`define RISCV_FORMAL_NRET 1 +`define RISCV_FORMAL_XLEN 32 +`define RISCV_FORMAL_ILEN 32 +`define RISCV_FORMAL_ALIGNED_MEM +`define RISCV_FORMAL_TRAP_ALIGNED_MEM +`include "rvfi_macros.vh" +`include "rvfi_channel.sv" +`include "rvfi_dmem_check.sv" + +module testbench ( + input clk +); + reg reset = 1; + + always @(posedge clk) + reset <= 0; + + + + + (* keep *) wire iBus_cmd_valid; + (* keep *) wire [31:0] iBus_cmd_payload_pc; + (* keep *) `rvformal_rand_reg iBus_cmd_ready; + (* keep *) `rvformal_rand_reg iBus_rsp_ready; + (* keep *) `rvformal_rand_reg [31:0] iBus_rsp_inst; + + + (* keep *) wire dBus_cmd_valid; + (* keep *) wire dBus_cmd_payload_wr; + (* keep *) wire [31:0] dBus_cmd_payload_address; + (* keep *) wire [31:0] dBus_cmd_payload_data; + (* keep *) wire [1:0] dBus_cmd_payload_size; + (* keep *) `rvformal_rand_reg dBus_cmd_ready; + (* keep *) `rvformal_rand_reg dBus_rsp_ready; + (* keep *) `rvformal_rand_reg [31:0] dBus_rsp_data; + + + `RVFI_WIRES + + (* keep *) wire [31:0] dmem_addr; + (* keep *) reg [31:0] dmem_data; + + rvfi_dmem_check checker_inst ( + .clock (clk ), + .reset (reset ), + .enable (1'b1 ), + .dmem_addr (dmem_addr), + `RVFI_CONN + ); + + (* keep *) reg dmem_last_valid; + (* keep *) wire [3:0] dBus_cmd_payload_mask; + + assign dBus_cmd_payload_mask = ((1 << (1 << dBus_cmd_payload_size))-1) << dBus_cmd_payload_address[1:0]; + + + + + always @(posedge clk) begin + if (reset) begin + dmem_last_valid <= 0; + end else begin + if(dmem_last_valid) begin + assume(dBus_rsp_data == dmem_data); + end + if(dBus_rsp_ready) begin + dmem_last_valid <= 0; + end + if(dBus_cmd_valid && dBus_cmd_ready) begin + if((dBus_cmd_payload_address >> 2) == (dmem_addr >> 2)) begin + if(!dBus_cmd_payload_wr) begin + dmem_last_valid <= 1; + end else begin + if (dBus_cmd_payload_mask[0]) dmem_data[ 7: 0] <= dBus_cmd_payload_data[ 7: 0]; + if (dBus_cmd_payload_mask[1]) dmem_data[15: 8] <= dBus_cmd_payload_data[15: 8]; + if (dBus_cmd_payload_mask[2]) dmem_data[23:16] <= dBus_cmd_payload_data[23:16]; + if (dBus_cmd_payload_mask[3]) dmem_data[31:24] <= dBus_cmd_payload_data[31:24]; + end + end + end + + end + + end + + + + + + VexRiscv uut ( + .clk (clk ), + .reset (reset ), + + .iBus_cmd_valid (iBus_cmd_valid), + .iBus_cmd_ready (iBus_cmd_ready), + .iBus_cmd_payload_pc (iBus_cmd_payload_pc ), + .iBus_rsp_ready(iBus_rsp_ready), + .iBus_rsp_inst (iBus_rsp_inst), + .iBus_rsp_error(1'b0), + + .dBus_cmd_valid(dBus_cmd_valid), + .dBus_cmd_payload_wr(dBus_cmd_payload_wr), + .dBus_cmd_payload_address(dBus_cmd_payload_address), + .dBus_cmd_payload_data(dBus_cmd_payload_data), + .dBus_cmd_payload_size(dBus_cmd_payload_size), + .dBus_cmd_ready(dBus_cmd_ready), + .dBus_rsp_ready(dBus_rsp_ready), + .dBus_rsp_data(dBus_rsp_data), + .dBus_rsp_error(1'b0), + + `RVFI_CONN + ); + +endmodule + From 082f8836a7c2db17d9e8d2cf251ecb8c3792d1ca Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sun, 26 Nov 2017 15:39:08 +0100 Subject: [PATCH 3/4] typo --- cores/VexRiscv/README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/cores/VexRiscv/README.md b/cores/VexRiscv/README.md index 70184ca..2cb40ec 100644 --- a/cores/VexRiscv/README.md +++ b/cores/VexRiscv/README.md @@ -12,7 +12,7 @@ All standards checks are passing - Causality - Liveness -Other tests passing : +Others tests passing : - Instruction Memory check - Data Memory check @@ -21,7 +21,7 @@ Other tests passing : First install Yosys, SymbiYosys, and the solvers. See [here](http://symbiyosys.readthedocs.io/en/latest/quickstart.html#installing) for instructions. -To run all checks: +To run all standards checks: ``` python3 ../../checks/genchecks.py @@ -39,7 +39,7 @@ export test=insn_beq_ch0; rm -r checks/$test; make -C checks -j$(nproc) $test/PA ``` -Running the memory checks : +To run imem/dmem checks checks : ``` sby -f imemcheck.sby From 2c26e75f37b3f43eb8e991951d779f4761d429a1 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sun, 26 Nov 2017 17:51:17 +0100 Subject: [PATCH 4/4] Fix sby relative paths --- cores/VexRiscv/dmemcheck.sby | 10 +++++----- cores/VexRiscv/imemcheck.sby | 11 +++++------ 2 files changed, 10 insertions(+), 11 deletions(-) diff --git a/cores/VexRiscv/dmemcheck.sby b/cores/VexRiscv/dmemcheck.sby index 9d0d49b..e8d9054 100644 --- a/cores/VexRiscv/dmemcheck.sby +++ b/cores/VexRiscv/dmemcheck.sby @@ -9,13 +9,13 @@ smtbmc --presat --unroll boolector [script] read_verilog -sv dmemcheck.sv -read_verilog /home/spinalvm/hdl/formal/riscv-formal/cores/VexRiscv/VexRiscv.v +read_verilog ../../VexRiscv.v prep -nordff -top testbench [files] dmemcheck.sv -/home/spinalvm/hdl/formal/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh -/home/spinalvm/hdl/formal/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv -/home/spinalvm/hdl/formal/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv -/home/spinalvm/hdl/formal/riscv-formal/cores/picorv32/../../checks/rvfi_dmem_check.sv +../../checks/rvfi_macros.vh +../../checks/rvfi_channel.sv +../../checks/rvfi_testbench.sv +../../checks/rvfi_dmem_check.sv diff --git a/cores/VexRiscv/imemcheck.sby b/cores/VexRiscv/imemcheck.sby index 2b6f0cc..6e48ac7 100644 --- a/cores/VexRiscv/imemcheck.sby +++ b/cores/VexRiscv/imemcheck.sby @@ -9,13 +9,12 @@ smtbmc --presat --unroll boolector [script] read_verilog -sv imemcheck.sv -read_verilog /home/spinalvm/hdl/formal/riscv-formal/cores/VexRiscv/VexRiscv.v +read_verilog ../../VexRiscv.v prep -nordff -top testbench [files] imemcheck.sv -/home/spinalvm/hdl/formal/riscv-formal/cores/picorv32/../../checks/rvfi_macros.vh -/home/spinalvm/hdl/formal/riscv-formal/cores/picorv32/../../checks/rvfi_channel.sv -/home/spinalvm/hdl/formal/riscv-formal/cores/picorv32/../../checks/rvfi_testbench.sv -/home/spinalvm/hdl/formal/riscv-formal/cores/picorv32/../../checks/rvfi_imem_check.sv - +../../checks/rvfi_macros.vh +../../checks/rvfi_channel.sv +../../checks/rvfi_testbench.sv +../../checks/rvfi_imem_check.sv