Personal
-dpv1 beside a laptop
-- An M.2 accelerator in a Thunderbolt enclosure with 1 GB of local resident memory. -
-The platform
-- dau accelerates the parts of Polars, dataframe, time-series, and analytical workflows that - suit streaming FPGA hardware. Reusable operations compose into right-sized configurations; - unsupported work stays in software. The same model scales from a personal accelerator to - multi-card systems. -
-Deployment model
-- The software model stays the same as capacity, memory, and physical placement change. -
-Personal
-- An M.2 accelerator in a Thunderbolt enclosure with 1 GB of local resident memory. -
-Scale-out
-- The host shards work across independent devices and merges results. Daisy-chained - devices share one Thunderbolt tunnel. -
-Workstation
-- A PCIe x8 development platform with 8 GB of local DDR3 for larger resident datasets. -
-Concept
-- A planned fabric-linked array with distributed resident memory and direct card-to-card - transport. -
-Personal computing
-- An accelerator for laptop and workstation development. Load a configuration that matches - the workflow you are running, without rebuilding the application around low-level hardware - APIs. -
-Portable · Flashable
-- High-performance systems -
-- Multiple accelerator cards partition data and workflows across independent local memory. - The platform is designed to grow resident capacity and analytical throughput from a - workstation to fabric-connected server arrays. -
-Parallel · Composable
-- Accelerate supported operations when hardware fits their semantics, data shape, and - performance needs. Keep everything else in software. -
-- Combine filtering, transformation, aggregation, partitioning, and domain operations into - streaming configurations shaped by measured workloads. -
-- Connect reconfigurable compute to dataframe and analytical interfaces instead of rewriting - workflows around low-level hardware APIs. -
-The dau flywheel
-- Measurements decide what runs in hardware today and what configuration gets built next. - Every deployed design goes through the same verification path. -
-Open source
-- Every part of the dau software stack is on GitHub under the Apache 2.0 license: the operator - tiles and their golden models, the build system, the simulator, the host driver, the - scheduler, and the Polars integration. You can read how a query becomes a design, build the - same bitstreams we run, and add your own tiles in your own package. -
-- Install straight from the repositories. The Polars package pulls in the rest. -
-pip install git+https://github.com/dau-dev/dau-polarsdau-polars
-- Capture a Polars plan, compile it onto tiles, run it on the device, the CPU, or split - between them. -
- - -dau-core
-- The operator tiles: SystemVerilog, bit-exact golden models, capability contracts, and the - registry. -
- - -dau-driver
-- Host I/O over XDMA on Linux and macOS: discovery, registers, DMA, and job execution. -
- - -dau-scheduler
-- Decides how much of a query the device takes, from measured costs. -
- - -dau-build
-- Declarative build specs through synthesis, programming, and smoke tests, with Vivado or - yosys. -
- - -dau-sim
-- Cycle-accurate simulation for Amaranth, SystemVerilog, and hand-built IR, with a cocotb - backend. -
- - - All repositories on GitHub - -- Design partner program -
-- We are working with early users and design partners on dau hardware, software, and - deployment. Tell us what you compute, where it runs, and how fast it needs to be. -
- -- Data. Accelerated. -
-- dau maps selected Polars, dataframe, time-series, and analytical operations into - reconfigurable FPGA dataflow and leaves the rest in software. The same model runs on a - personal accelerator beside your laptop and on data-center-scale systems. -
- -From proof to platform
-- dau began on dpv1 with a 5 GB NYSE TAQ dataset and a concrete task: calculate OHLCV bars. - Staged resident, repeated queries ran in 0.92 seconds against 1.5 seconds on the CPU—39% - lower per-query latency, every result matched to the software golden. dpv2 is commodity - hardware doing real work: a consumer-grade FPGA card that costs about $700, in a - consumer-grade desktop with a quad-core Intel Core i7. With a six-million-row table resident - on the card, Polars and the card working the same scan together finished in 4.2 ms against - 10.4 ms for the CPU alone, using all of its threads. That is 2.5x faster, and every result - matched the software golden at every one of the 164 split points we measured. The scheduler - chose the split from measured costs; nobody tuned it by hand. -
-- dpv1 · Where it started -
-First platform
-134K LUTs · 1 GB DDR3
-- Established the core result: resident analytical queries can outperform CPU execution on - hardware you can put beside a laptop. -
-- dpv2 · Current platform -
-Running today
-204K LUTs · 10 GB DDR3 · PCIe x8
-- Two memory systems (2 GB onboard for bandwidth, 8 GB SODIMM for resident capacity) and - eight parallel lanes. CPU and card together: 2.5x the CPU alone on a resident scan, - bit-exact. -
-dpv3 · Planned
-In design
-- 663K LUTs · 32–128 GB DDR4 · PCIe Gen3 x8 · Fabric links -
-- A concept design for fabric-connected arrays with distributed resident memory. -
-{board.summary}
+Personal
+A Thunderbolt device connected to your laptop.
+Scale-out
++ Several Thunderbolt devices connected to one laptop, with work split across them. +
+Workstation
+A PCIe card in your desktop.
+Planned
+Several PCIe cards in a server, linked directly to each other.
+| Benchmark | +Board | +Result | +
|---|---|---|
| {r.benchmark} | +{r.board} | +
+ {r.outcome} +{r.detail} + |
+
Draft
+
+ Items marked TBD have not been set. They live in src/lib/invest/overview.ts; the
+ results come from src/lib/results.ts, shared with the home page.
+
+ dau builds FPGA accelerators sized to analytical workloads, along with open-source software that decides how much of + each query the FPGA should run. +
+01 · Thesis
++ Analytical software already runs on fast CPUs. dau adds an FPGA card to the machine and splits the work between + the two, so queries run faster without rewriting the software. +
++ dau loads rows into device memory once and runs repeated filter, derive, and aggregate queries against them. A + cost model picks the split for each query from measured rates. Anything the loaded hardware can't do runs on the + CPU, and the planner reports it. +
+Sorts, text search, floating point, and everything else.
+ {/snippet} + {#snippet hardware()} +Scans over resident rows.
+ {/snippet} +02 · What exists
+03 · Evidence
++ *On TPC-H query 6, a standard analytics benchmark, adding a dau card to the host made the query about 2.5× faster. + Every figure matches its software reference exactly. +
+04 · Business model
++ The software is Apache 2.0, published on PyPI, and runs on open FPGA hardware. Revenue comes from boards built for + dau and from configurations we build and verify for a customer's workloads. +
+05 · Market
++ The first workloads are time-series and market data: bars, windows, and as-of joins run again and again over the + same history. +
+06 · Roadmap
+07 · Risk
+08 · The ask
++ Questions and data-room requests: {CONTACT} +
++ dau runs selected Polars, dataframe, and time-series operations as FPGA dataflow and leaves the rest in software. + The same software works with an accelerator next to your laptop or a card in a server. +
+Scans run on the FPGA.
++ Filters, derived columns, and aggregations stream through tiles built for the workload. Rows can stay in device + memory between queries. +
+ {/snippet} + {#snippet software()} +Everything else runs in Polars.
++ If the loaded configuration doesn't cover an operation, it runs on the CPU, and the planner reports what ran + where. +
+ {/snippet} +Platform
++ Configurations are assembled from reusable operations and sized to the job. Your code stays the same whether it + runs on one accelerator next to a laptop or several cards in a server. +
++ We measure real workloads to decide what runs in hardware now and what to build next. Every design is verified + the same way before it ships. +
+Results
++ *On TPC-H query 6, a standard analytics benchmark, adding a dau card to the host made the query about 2.5× + faster. The table below lists benchmarks we have run on our boards. Every result matches the software reference + exactly. +
+Open source
++ The operator tiles and their reference models, the build system, the simulator, the host driver, and the + scheduler are Apache 2.0 licensed and published on GitHub and PyPI. They run on open FPGA hardware, so you can + build the same bitstreams we run and add tiles in your own package. Boards built for dau are available through + the design partner program. The Polars integration will be released soon. +
+ + +pip install dau-core dau-driver dau-schedulerDesign partners
++ We're working with early users on dau hardware, software, and deployment. Tell us what you compute, where it runs, + and how fast it needs to be. +
+Privacy
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