diff --git a/chips/index.html b/chips/index.html index 9304628..1926354 100644 --- a/chips/index.html +++ b/chips/index.html @@ -3,125 +3,172 @@ -Inside the Machines — CPU vs GPU vs DPU, Exploded | JC Davis - +CPU vs GPU vs DPU — Exploded in 3D | JC Davis + - + - - + + @@ -130,211 +177,149 @@ JC Davis
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Interactive deep dive

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Inside the Machines: CPU vs GPU vs DPU, Exploded

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Three processors, pulled apart layer by layer in 3D. Same silicon technology, wildly different physical makeup — because each one is built to win a different race. Drag the explode slider, tap any part, and switch the explanation depth from ELI5 to expert.

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Exploded in 3D

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CPU · GPU · DPU, taken apart

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Drag to orbit. Hover any block. Click to pin it. Compare component classes below.

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Three packages, side by side, exploded

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Stylized schematic models (not to scale). CPU = AMD EPYC 9654 “Genoa” (2022) · GPU = NVIDIA H100 SXM5 “GH100” (2022) · DPU = NVIDIA BlueField-3 (2022). Drag to orbit, scroll the slider to explode, tap any block to learn what it does.

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This 3D view needs WebGL. The written deep dive below covers every part in full.

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Tip: pick a component class to spotlight it on all three chips at once — the cards below explain how each chip builds it, and why they differ.

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GPUGH100 compute die

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Meet the three machines

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Same underlying technology — transistors etched into silicon. Completely different bodies, because each serves a different master.

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The CPU

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AMD EPYC 9654 “Genoa” · 2022 · server processor

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  • 96 cores / 192 threads · 12 chiplets + 1 I/O die
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  • 384 MB L3 cache · 96 MB L2 · 12× DDR5
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  • Socket SP5 (LGA-6096) · up to 400 W
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  • ≈13B transistors (est.)
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The GPU

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NVIDIA H100 SXM5 “GH100” · 2022 · AI accelerator

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  • 132 SMs · 16,896 CUDA cores · 528 Tensor Cores
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  • 50 MB L2 · 80 GB HBM3 @ ~3 TB/s
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  • NVLink 900 GB/s · 700 W · TSMC 4N
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  • 80B transistors · 814 mm² die
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The DPU

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NVIDIA BlueField-3 · 2022 · data processing unit

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  • 16× Arm Cortex-A78 · 16× DPA cores
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  • 400 Gb/s networking · PCIe Gen5 ×32
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  • Up to 64 GB DDR5 · 42 SPECrate2017_int
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  • 22B transistors
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WebGL isn't available in this browser, so the 3D stage can't render.
The comparison cards and spec tables below still work.

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Layer by layer: what you're looking at

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Every chip in the 3D view is the same seven-layer sandwich, top to bottom. What changes is what each layer is for.

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Heat spreader / lid

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Thermal paste layer

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The silicon die(s)

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Interposer (GPU only)

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Package substrate

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Pins / pads / balls

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Transistors (the bottom of the rabbit hole)

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Component diff

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Compare

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What it is

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CPU

AMD EPYC 9654 “Genoa”

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GPU

NVIDIA H100 SXM5 “GH100”

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DPU

NVIDIA BlueField-3

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Side-by-side: what each has, what each lacks, and why

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The physical differences aren't accidents — each missing piece is a deliberate trade. Tap the level switcher above to change the depth of the whole page.

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At a glance

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The same seven component classes, one row each. The pattern: every chip spends its transistor budget on the thing its job demands most.

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Physical componentCPU (Genoa)GPU (H100)DPU (BlueField-3)
Primary compute units✔ 96 big out-of-order cores — few, brilliant, branchy✔ 132 SMs / 16,896 simple cores — an army doing the same op✔ 16 Arm A78 cores — modest, for control-plane software
Matrix / AI accelerators✘ none dedicated — AVX-512 covers vectors; die budget goes to cache + OoO logic✔ 528 Tensor Cores + Transformer Engine — the whole point of the chip✘ none — 1.5 TOPS is incidental; it steers data, doesn't train on it
Packet / crypto / storage engines✘ none — handling packets in software wastes precious general-purpose cores✘ none — every mm² is for FLOPS; networking lives on the DPU next door✔ the whole point — RDMA, NVMe-oF, IPsec/TLS, virtual switching in hardware
Cache hierarchy✔ huge — 96 MB L2 + 384 MB L3 to hide memory latency for unpredictable code✔ 50 MB L2 only, no L3 — thousands of threads hide latency; SRAM budget → more SMs✔ small coherent caches on a mesh — control-plane code, not number-crunching
Memory system✔ 12× DDR5 channels, DIMMs off-package — terabytes of capacity, modest bandwidth✔ 80 GB HBM3 on-package — ~3 TB/s bandwidth, capacity capped by stack count✔ up to 64 GB DDR5 on-card — packet buffers and OS, not datasets
Chip-to-chip interconnect✔ Infinity Fabric + 128× PCIe Gen5 — talks to everything: RAM, GPUs, DPUs, disks✔ NVLink 900 GB/s — GPUs gossip with GPUs at memory speed; CPU link is secondary✔ 400 Gb/s Ethernet/InfiniBand — the DPU is the network endpoint for the server
Package style✔ 13-chiplet MCM, socketed LGA-6096 — yield: small dies, mix-and-match, replaceable✔ one giant monolithic die + HBM on silicon interposer — SM-to-SM bandwidth forbids chiplet hops✔ single SoC + heatsink on a card — integration beats raw speed; it must be cheap per server
Runs an OS / apps✔ yes — the OS lives here✘ no — it runs kernels the CPU launches; no OS, no interrupts✔ yes — its own Linux (DOCA) — it's an independent computer in front of the computer
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Component classCPU — EPYC 9654GPU — H100DPU — BlueField-3
⚙ Compute cores96× Zen 4general-purpose, branchy code132 SMs · 16,896 CUDAmassively parallel math16× Arm A78 + 16 DPAcontrol plane + packet I/O
🗄 Cache hierarchy96 MB L2 + 384 MB L3hide DRAM latency for random access50 MB shared L2rendezvous for 132 SMs, streaming datamodest L2/L3 on meshpackets stream through, not cached
🧠 Memory system12-ch DDR5, 461 GB/shuge capacity (TBs), moderate speed5× HBM3, 3.35 TB/sbandwidth at all costs; 80 GB is enough1 DDR5 ctrl, 16–32 GBjust a control plane; packets bypass RAM
🔗 InterconnectInfinity Fabric via sIODglue 12 chiplets into one CPUCoWoS interposer + NVLink 900 GB/sfeed SMs; scale to 256 GPUsPCIe Gen5 switch (32 lanes)own devices on the bus, bypass host
🌐 Network I/O— none on diethat's the DPU's job— none on dieNVLink is GPU-to-GPU, not networkConnectX-7 · 400 GbEthe whole point of the chip
🚀 AcceleratorsAVX-512 in-corevector math, no extra blocks528 4th-gen Tensor Coresthe chip IS the acceleratorcrypto · RegEx · NVMe-oFinfrastructure tax, in fixed logic
📦 PackageLGA-6096, socketedfield-replaceable server CPUSXM5 mezzanine, 700 Wpower + NVLink no slot can carryBGA card, air-cooledcheap, permanent, one per server
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Provenance & honesty notes

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Provenance

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Models are schematic — block sizes show hierarchy, not exact floorplans. Every headline number was verified against vendor or press sources, Sep 2026; anything estimated is labeled as an estimate.

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Chips shown: AMD EPYC 9654 “Genoa” (Zen 4, launched Nov 2022) · NVIDIA H100 SXM5 “GH100” (Hopper, announced Mar 2022) · NVIDIA BlueField-3 DPU (announced Apr 2021, shipping 2022).

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Key figures verified Sep 2026: GH100 — 80B transistors, 814 mm², TSMC 4N, 144 SMs on die (132 in H100 SXM5 product), 16,896 FP32 CUDA cores, 50 MB L2, 80 GB HBM3, NVLink 900 GB/s (TechPowerUp, TechPowerUp). BlueField-3 — 22B transistors, 16× Arm Cortex-A78, 16 DPA cores, 400 Gb/s, PCIe Gen5 ×32, ≤64 GB DDR5, 42 SPECrate2017_int (NVIDIA technical blog, Tom's Hardware). EPYC Genoa — 96 cores/192 threads, 12× 5 nm CCDs + 6 nm sIOD, 384 MB L3, 12× DDR5, 128 PCIe Gen5 lanes, SP5 LGA-6096 (TechPowerUp).

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Estimates, labeled as such: Genoa transistor count (≈13B — AMD never published a figure); BlueField-3 process node (7nm-class — NVIDIA undisclosed). The 3D models are stylized schematics, not to scale and not die shots.

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  • AMD EPYC 9654 “Genoa” — 96C/192T Zen 4 (12 CCDs × 8 cores), 1 MB L2/core, 32 MB L3/CCD (384 MB), 5 nm CCDs + 6 nm 397 mm² sIOD, 12-ch DDR5-4800 (460.8 GB/s), 128× PCIe Gen5, SP5 LGA-6096, 360 W. TechPowerUp specs; CCD/CCX layout via Tom's Hardware.
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  • NVIDIA H100 SXM5 “GH100” — full die 144 SMs (132 enabled), 128 CUDA + 4 Tensor cores/SM, 50 MB L2, 5 active HBM3 stacks of 6 on package, 5120-bit, 80 GB, ~3.35 TB/s, 80B transistors, 814 mm² TSMC 4N, 4th-gen NVLink 900 GB/s, 700 W. TechPowerUp specs; TweakTown; HWCooling (5-of-6 stacks).
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  • NVIDIA BlueField-3 — 22B transistors, 16× Arm A78 v8.2 on coherent mesh, ConnectX-7 400 GbE/NDR, 4× crypto acceleration, 16 DPA packet cores, PCIe Gen5 switch, 1 DDR5 controller (16/32 GB on-card), inline IPsec/TLS, RegEx, NVMe-oF offload. NVIDIA technical blog; NVIDIA docs.
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  • Exploded-stack geometry, pad counts, and internal block placement are estimates for illustration — vendors don't publish package CAD.
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Provenance & honesty notes

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← JC Davis · An interactive explainer. Models are schematic; specs verified against vendor/press sources, Sep 2026.

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← JC Davis · CPU vs GPU vs DPU, exploded. Schematic models; specs verified Sep 2026.

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