risc-v
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
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MDX — A BSD-style RTOS
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Jun 2, 2024 - C
WIP: Very much a RISC-V core, written in SystemVerilog
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Jun 2, 2024 - SystemVerilog
C++20 RISC-V RV32/64/128 userspace emulator library
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Jun 2, 2024 - C++
Speech-to-text, text-to-speech, and speaker recongition using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, Raspberry Pi, RISC-V, x86_64 servers, websocket server/client, C/C++, Python, Kotlin, C#, Go, NodeJS, Java, Swift
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Jun 2, 2024 - C++
GTKWave Decoders for RISCV
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Jun 2, 2024 - C++
RT-Thread is an open source IoT real-time operating system (RTOS).
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Jun 2, 2024 - C
RISC-V CPU simulator for education purposes
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Jun 1, 2024 - C++
The official repository for the gem5 computer-system architecture simulator.
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Jun 1, 2024 - C++