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Pull requests: OpenXiangShan/XiangShan
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DCache: Move L2 refill error signal to refill_info
#3063
opened Jun 12, 2024 by
bosscharlie
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IssueQueue: when src0-2 read vector reg #0, transfer to src3 to read v0
#3060
opened Jun 12, 2024 by
sinsanction
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vset: fix old vl read for vsetvl and vsetvli instructions
#3058
opened Jun 11, 2024 by
Ziyue-Zhang
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vfalu: Use oldVd as input to mgu in last Uop for vfred inst
#3056
opened Jun 11, 2024 by
sinceforYy
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Revert "LSQ: optimize static clock gating coverage (#3023)"
#3055
opened Jun 11, 2024 by
Tang-Haojin
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L1CacheErrorInfo: code refactor for correct and convenient clockgate
refactor
Just make code pretty
security
Some designs may introduce security issues
#3044
opened Jun 5, 2024 by
Maxpicca-Li
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IFU: fix the bug of postponing MMIO instruction fetch strategy
#3038
opened Jun 4, 2024 by
my-mayfly
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Backend fixtiming: fix rab/exuwb/wbtorob timing
timing
Fix bad timing
#3032
opened Jun 3, 2024 by
lewislzh
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memblock: add rest clockgate of reg.
power
about power design or optimization
#3017
opened May 28, 2024 by
Maxpicca-Li
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exception: check high bits of target in brh and jmp
#3003
opened May 23, 2024 by
Tang-Haojin
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Merge ftb low power & fix fallThroughAddr calculation.
#2997
opened May 21, 2024 by
sleep-zzz
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ftb:Higher register function merging. (higher regs clock gating efficiency)
#2981
opened May 13, 2024 by
sleep-zzz
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wpu:fix the issue of abnormal power
power
about power design or optimization
#2976
opened May 13, 2024 by
Maxpicca-Li
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Memblock: Merge memblock timing fixes into master
timing
Fix bad timing
#2917
opened Apr 24, 2024 by
cz4e
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